Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A power amplifier system includes a first power detector configured to detect a forward power output of a power amplifier, the first power detector configured to provide a first power detector output and an adjustable load coupled to the output of the power amplifier and configured to receive the first power detector output, the adjustable load configured to provide an adjustable impedance at the output of the power amplifier in response to one of the output of the power amplifier and the first power detector output.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: According to one exemplary embodiment, a switching module includes a first harmonic phase tuning filter coupled to a first input of an RF switch. The first harmonic phase tuning filter is configured to provide an output impedance that substantially matches an input impedance of the RF switch at approximately a fundamental frequency and to provide a high impedance at approximately a harmonic frequency generated by the RF switch. The first harmonic phase tuning filter includes an LC circuit coupled between input and output terminals of the first harmonic phase tuning filter and tuned to provide the high impedance at approximately the harmonic frequency generated by the RF switch. The RF switching module further includes a second harmonic phase tuning filter coupled to a second input of the RF switch. The first and second harmonic phase tuning filters can be fabricated on a single semiconductor die.

Abstract: According to one exemplary embodiment, a switching device with phase selection terminals to select between at least two phase shifting modes to reduce intermodulation distortion in the switching device includes a first phase selection terminal to select a first phase shifting mode of the switching device by enabling a first phase shifter in a first phase shifting switching branch coupled to an input of the switching device. The switching device further includes a second phase selection terminal to select a second phase shifting mode of the switching device by enabling a second phase shifting switching branch coupled to the switching device input. The intermodulation distortion in the switching device is reduced by selecting one of the first and second phase shifting modes. The switching device may further include a number of FETs coupled in series between an output of the switching device and the first and second phase shifting switching branches.

Abstract: According to one exemplary embodiment, a switching module includes a first harmonic phase tuning filter coupled to a first input of an RF switch. The first harmonic phase tuning filter is configured to provide an output impedance that substantially matches an input impedance of the RF switch at approximately a fundamental frequency and to provide a low impedance at approximately a harmonic frequency generated by the RF switch. The first harmonic phase tuning filter includes an LC circuit coupled between an output terminal of the first harmonic phase tuning filter and a ground and tuned to provide the low impedance at approximately the harmonic frequency generated by the RF switch. The RF switching module further includes a second harmonic phase tuning filter coupled to a second input of the RF switch. The first and second harmonic phase tuning filters can be fabricated on a single semiconductor die.

Abstract: According to one exemplary embodiment, a switching device with phase selection terminals to select between at least two phase shifting modes to reduce intermodulation distortion in the switching device includes a first phase selection terminal to select a first phase shifting mode of the switching device by enabling a first transmission line in a first phase shifting switching branch coupled to an input of the switching device. The switching device further includes a second phase selection terminal to select a second phase shifting mode of the switching device by enabling a second phase shifting switching branch coupled to the switching device input. The intermodulation distortion in the switching device is reduced by selecting one of the first and second phase shifting modes. The first transmission line is enabled by enabling a FET coupled in series with the first transmission line in the first phase shifting switching branch.

Abstract: A power amplifier system includes a first power detector configured to detect a forward power output of a power amplifier, the first power detector configured to provide a first power detector output and an adjustable load coupled to the output of the power amplifier and configured to receive the first power detector output, the adjustable load configured to provide an adjustable impedance at the output of the power amplifier in response to one of the output of the power amplifier and the first power detector output.

Abstract: According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

Abstract: According to one exemplary embodiment, a switching device with phase selection terminals to select between at least two phase shifting modes to reduce intermodulation distortion in the switching device includes a first phase selection terminal to select a first phase shifting mode of the switching device by enabling a first transmission line in a first phase shifting switching branch coupled to an input of the switching device. The switching device further includes a second phase selection terminal to select a second phase shifting mode of the switching device by enabling a second phase shifting switching branch coupled to the switching device input. The intermodulation distortion in the switching device is reduced by selecting one of the first and second phase shifting modes. The first transmission line is enabled by enabling a FET coupled in series with the first transmission line in the first phase shifting switching branch.

Abstract: According to one exemplary embodiment, a switching device with phase selection terminals to select between at least two phase shifting modes to reduce intermodulation distortion in the switching device includes a first phase selection terminal to select a first phase shifting mode of the switching device by enabling a first phase shifter in a first phase shifting switching branch coupled to an input of the switching device. The switching device further includes a second phase selection terminal to select a second phase shifting mode of the switching device by enabling a second phase shifting switching branch coupled to the switching device input. The intermodulation distortion in the switching device is reduced by selecting one of the first and second phase shifting modes. The switching device may further include a number of FETs coupled in series between an output of the switching device and the first and second phase shifting switching branches.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: According to one exemplary embodiment, a switching module includes a first harmonic phase tuning filter coupled to a first input of an RF switch. The first harmonic phase tuning filter is configured to provide an output impedance that substantially matches an input impedance of the RF switch at approximately a fundamental frequency and to provide a low impedance at approximately a harmonic frequency generated by the RF switch. The first harmonic phase tuning filter includes an LC circuit coupled between an output terminal of the first harmonic phase tuning filter and a ground and tuned to provide the low impedance at approximately the harmonic frequency generated by the RF switch. The RF switching module further includes a second harmonic phase tuning filter coupled to a second input of the RF switch. The first and second harmonic phase tuning filters can be fabricated on a single semiconductor die.

Abstract: According to one exemplary embodiment, a switching module includes a first harmonic phase tuning filter coupled to a first input of an RF switch. The first harmonic phase tuning filter is configured to provide an output impedance that substantially matches an input impedance of the RF switch at approximately a fundamental frequency and to provide a high impedance at approximately a harmonic frequency generated by the RF switch. The first harmonic phase tuning filter includes an LC circuit coupled between input and output terminals of the first harmonic phase tuning filter and tuned to provide the high impedance at approximately the harmonic frequency generated by the RF switch. The RF switching module further includes a second harmonic phase tuning filter coupled to a second input of the RF switch. The first and second harmonic phase tuning filters can be fabricated on a single semiconductor die.

Abstract: According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

Abstract: A uniform tailored electrical field in a multigate field effect D-mode transistor is automatically provided by a feedback circuit which couples drain bias voltages to the gates of a multigate transistor to bias the gates incrementally such that the highest voltage is applied to the gate nearest the drain while the lowest voltage is applied to the gate nearest the source. E-mode multigate FET's carry higher gate voltage on the gate close to the source compared to a gate voltage on a last gate, located close to the drain. The proper distribution of gate voltages improves the transconductance G.sub.m of the transistor and decreases gate capacitance C.sub.gs, which increases the speed of operation of a multigate FETs.