Abstract: A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.

Abstract: A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.

Abstract: A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.

Abstract: A semiconductor device having: a semiconductor substrate; an isolation trench formed in a surface portion of the semiconductor substrate and defining an NMOSFET active region and a PMOSFET active region; a silicon oxide film burying only a lower portion of the isolation trench and defining a recess above the lower portion; an NMOSFET structure formed in the NMOSFET active region and having an insulated gate electrode structure and n-type source/drain regions; a PMOSFET structure formed in the PMOSFET active region and having an insulated gate electrode structure and p-type source/drain regions; a tensile stress film covering the NMOSFET structure and extending to the recess surrounding the NMOSFET active region and to the recess outside the PMOSFET active region along a gate width direction; and a compressive stress film covering the PMOSFET structure and extending to the recess outside the PMOSFET active region along a channel length direction.

Abstract: A method for manufacturing a semiconductor device includes forming a first stress film covering a first transistor arranged in a first region and a second transistor arranged in a second region on a semiconductor substrate; forming an etching stopper film, which possesses etching characteristics different from etching characteristics of the first stress film, on the first stress film; etching the etching stopper film to selectively leave the etching stopper film at a portion covering a sidewall portion of the first stress film in the first region; removing both the etching stopper film and the first stress film in the second region; and forming a second stress film, which possesses etching characteristics different from the etching characteristics of the etching stopper film, on the semiconductor substrate in such a manner as to cover the second transistor, the first stress film.

Abstract: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.

Abstract: A method of manufacturing a semiconductor device includes forming a Metal Insulator Semiconductor (MIS) transistor over a semiconductor substrate, forming a nickel silicide layer on a surface of source/drain region of the MIS transistor, the nickel silicide layer containing platinum or tungsten, forming a stress film over the surface of the MIS transistor, and selectively removing the stress film so as to expose at least a part of the nickel silicide layer on the surface of source/drain region.

Abstract: A semiconductor device having: a semiconductor substrate; an isolation trench formed in a surface portion of the semiconductor substrate and defining an NMOSFET active region and a PMOSFET active region; a silicon oxide film burying only a lower portion of the isolation trench and defining a recess above the lower portion; an NMOSFET structure formed in the NMOSFET active region and having an insulated gate electrode structure and n-type source/drain regions; a PMOSFET structure formed in the PMOSFET active region and having an insulated gate electrode structure and p-type source/drain regions; a tensile stress film covering the NMOSFET structure and extending to the recess surrounding the NMOSFET active region and to the recess outside the PMOSFET active region along a gate width direction; and a compressive stress film covering the PMOSFET structure and extending to the recess outside the PMOSFET active region along a channel length direction.

Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a wiring layer over a substrate, forming a first film over the wiring layer, forming a second film over the first film, selectively etching the first and second films to form an first end of the first and second films over the wiring layer, forming a third film over the second film, selectively etching the third film to form a second end of the third film tapered off over the first end of the first and second films, forming an interlayer insulating film over the second and third films, forming a contact hole by selectively etching the interlayer insulating film, the first film, the second film and the third film, and forming a contact plug connected to the wiring layer in the contact holes.

Abstract: A semiconductor device wherein the same metal gate material is used for both an n-channel CMOS transistor and a p-channel CMOS transistor and a manufacturing method therefor are disclosed. The n-channel transistor includes an impurity region, a first gate laminated body that has a gate oxide film and a gate electrode but does not have a gate electrode sidewall insulating film, and a first silicon nitride film that has a tensile stress and covers the surface of a semiconductor substrate and the first gate laminated body. The p-channel transistor includes an impurity region; a second gate laminated body that has a gate oxide film, a gate electrode, and a gate electrode sidewall insulating film; and a second silicon nitride film that has a compressive stress and covers the surface of the semiconductor substrate and the second gate laminated body.

Abstract: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.

Abstract: A CMOS semiconductor device includes: an isolation region formed in the surface layer of a semiconductor substrate to define an NMOSFET active region and a PMOSFET active region adjacent to each other; an NMOSFET structure formed in the NMOSFET active region; a PMOSFET structure formed in the PMOSFET active region; a tensile stress film covering the NMOSFET structure; and a compressive stress film covering the PMOSFET structure, wherein a border between the tensile stress film and the compressive stress film is set nearer to the PMOSFET active region than the NMOSFET active region along a gate width direction. A performance of a CMOS semiconductor device can be improved by the layout of the tensile and compressive stress films.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.