Patents by Inventor Sergey R. Shevtsov

Sergey R. Shevtsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating point addition methods and apparatus
    Patent number: 5808926
    Abstract: A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit") does not. The result of the rounding subunit is selected as the addition result when one of the following conditions (R1), (R2), (R3) is true: (R1) the operation is an effective addition; (R2) the operation is an effective subtraction, the magnitude ED of the difference between the exponents of the operands is 1, and normalization of the result is not required; (R3) the operation is an effective subtraction and ED>1. The addition result is selected from the non-rounding subunit in the remaining cases. In some embodiments, the rounding subunit overlaps rounding with adding the operands, significands. In some embodiments, the addition unit satisfies ANSI/IEEE Standard 754-1985.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: September 15, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Valery Y. Gorshtein, Anatoly I. Grushin, Sergey R. Shevtsov