Patents by Inventor Sergey S. Ryabchenkov

Sergey S. Ryabchenkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sample-and-hold (S/H) circuit
    Patent number: 7973570
    Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: July 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John M. Pigott, Sergey S. Ryabchenkov
  • SAMPLE-AND-HOLD (S/H) CIRCUIT
    Publication number: 20100164551
    Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).
    Type: Application
    Filed: August 14, 2009
    Publication date: July 1, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: John M. Pigott, Sergey S. Ryabchenkov