Patents by Inventor Sergey Shumarayev

Sergey Shumarayev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques For Providing Option Conductors to Connect Components in an Oscillator Circuit
    Publication number: 20100090774
    Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
    Type: Application
    Filed: November 25, 2008
    Publication date: April 15, 2010
    Applicant: Altera Corporation
    Inventors: Sergey Shumarayev, Wilson Wong, Allen Chan, Ali Atesoglu
  • Programmable receiver equalization circuitry and methods
    Patent number: 7697600
    Abstract: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 13, 2010
    Assignee: Altera Corporation
    Inventors: Simardeep Maangat, Sergey Shumarayev, Wilson Wong, ThuNgoc Tran
  • Automatic calibration in high-speed serial interface receiver circuitry
    Publication number: 20100086017
    Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 8, 2010
    Inventors: Sergey Shumarayev, Wilson Wong
  • Systems and methods for simulating link performance
    Patent number: 7693691
    Abstract: Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform may simulate link performance using transceiver behavioral models (e.g., transmitter and receiver behavioral models) that incorporate silicon level parameters, which parameters enable the behavioral models to substantially emulate the actual behavior of the transceiver portions of the link.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: April 6, 2010
    Assignee: Altera Corporation
    Inventors: Yuming Tao, William W. Bereza, Rakesh H. Patel, Tad Kwasniewski, Sergey Shumarayev, Shoujun Wang, Miao Li
  • High-speed serial interface circuitry for programmable logic device integrated circuits
    Patent number: 7688106
    Abstract: High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: March 30, 2010
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Thungoc M. Tran, Simardeep Maangat, Wilson Wong
  • Techniques For Generating Fractional Clock Signals
    Publication number: 20100073094
    Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 25, 2010
    Applicant: Altera Corporation
    Inventors: Tim Tri Hoang, Wilson Wong, Sergey Shumarayev
  • Dynamically-adjustable differential output drivers
    Patent number: 7675326
    Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 9, 2010
    Assignee: Altera Corporation
    Inventors: Mei Luo, Sergey Shumarayev, Wilson Wong, Chong H. Lee
  • HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES
    Publication number: 20100058099
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Application
    Filed: October 9, 2009
    Publication date: March 4, 2010
    Applicant: ALTERA CORPORATION
    Inventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
  • Variable external interface circuitry on programmable logic device integrated circuits
    Patent number: 7659745
    Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: February 9, 2010
    Assignee: Altera Corporation
    Inventors: Wilson Wong, Sergey Shumarayev, Thungoc M. Tran, Tim Tri Hoang
  • Techniques for power management on integrated circuits
    Patent number: 7638990
    Abstract: A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.
    Type: Grant
    Filed: May 27, 2007
    Date of Patent: December 29, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Simardeep Maangat
  • Phase frequency detectors generating minimum pulse widths
    Patent number: 7633349
    Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: December 15, 2009
    Assignee: Altera Corporation
    Inventors: Tim Tri Hoang, Sergey Shumarayev, Wanli Chang
  • INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER
    Publication number: 20090302888
    Abstract: Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Applicant: ALTERA CORPORATION
    Inventors: Sergey Shumarayev, Thungoc M. Tran, Wilson Wong, Simardeep Maangat
  • INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    Publication number: 20090289660
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Application
    Filed: January 20, 2009
    Publication date: November 26, 2009
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • SIGNAL ADJUSTMENT RECEIVER CIRCUITRY
    Publication number: 20090284292
    Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
    Type: Application
    Filed: July 28, 2009
    Publication date: November 19, 2009
    Applicant: Altera Corporation
    Inventors: Wilson Wong, Rakesh H. Patel, Sergey Shumarayev, Tin H. Lai
  • SIGNAL ADJUSTMENT RECEIVER CIRCUITRY
    Publication number: 20090285275
    Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
    Type: Application
    Filed: July 28, 2009
    Publication date: November 19, 2009
    Applicant: Altera Corporation
    Inventors: Wilson Wong, Rakesh H. Patel, Sergey Shumarayev, Tin H. Lai
  • Techniques for compensating delays in clock signals on integrated circuits
    Patent number: 7619451
    Abstract: Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.
    Type: Grant
    Filed: February 3, 2007
    Date of Patent: November 17, 2009
    Assignee: Altera Corporation
    Inventors: Tim Tri Hoang, Sergey Shumarayev, Kazi Asaduzzaman, Wanli Chang, Mian Z. Smith, Kang-Wei Lai, Leon Zheng
  • Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    Patent number: 7616657
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: November 10, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Bill W Bereza, Chong H Lee, Rakesh H Patel, Wilson Wong
  • PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION
    Publication number: 20090257445
    Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Applicant: Altera Corporation
    Inventors: Allen Chan, Sergey Shumarayev, Wilson Wong, Weiqi Ding
  • Flexible high-speed serial interface architectures for programmable integrated circuit devices
    Patent number: 7602212
    Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 13, 2009
    Assignee: Altera Corporation
    Inventors: Allen Chan, Sergey Shumarayev, Wilson Wong
  • Flexible signal detect for programmable logic device serial interface
    Patent number: 7589651
    Abstract: A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used in each receiver and each transmitter in each serial interface on the PLD. Alternatively, time division multiplexing can be used to allow the receiver and transmitter in each receiver/transmitter pair, or even multiple receiver/transmitter pairs, to share a single ADC. When none of the receiver/transmitter pairs associated with a particular ADC is being used, the ADC can be accessed for use simply as an ADC.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: September 15, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Rakesh H. Patel, Wilson Wong