Abstract: A circuit and method for an audio op-amp that is configured to minimize crossover distortion between push and pull components of the audio op-amp. The audio op-amp includes an input stage that receives differential input signals and generates an output that amplifies the difference between the input signals. The audio op-amp further includes an output stage that receive the amplified signal and generate an audio output signal for playback by a speaker system. The output stage includes a diamond driver circuit that buffers the input stage from the speaker system, a boost circuit that includes a pair of boosting transistors that amplify the current of the amplified signal, and a biasing circuit that provides bias currents to the transistors of the boost circuit in a manner that minimizes crossover distortion between the boosting transistors.

Abstract: A circuit and method for an audio op-amp that is configured to minimize crossover distortion between push and pull components of the audio op-amp. The audio op-amp includes an input stage that receives differential input signals and generates an output that amplifies the difference between the input signals. The audio op-amp further includes an output stage that receive the amplified signal and generate an audio output signal for playback by a speaker system. The output stage includes a diamond driver circuit that buffers the input stage from the speaker system, a boost circuit that includes a pair of boosting transistors that amplify the current of the amplified signal, and a biasing circuit that provides bias currents to the transistors of the boost circuit in a manner that minimizes crossover distortion between the boosting transistors.

Abstract: Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J2) and second (J4) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J2), and second input signal (Vin?) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J1) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.

Abstract: A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.

Abstract: An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.

Abstract: Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first one of the first and second electrodes of the second transistor being coupled to receive a second signal.

Abstract: An amplifier (10) includes a first stage (4) including differentially coupled first (Q1) and second (Q2) input transistors and a controlled active load circuit (6). A second stage (8) includes differentially coupled third (Q5) and fourth (Q6) input transistors and a load circuit (Q7,8). A first output (2A) of the first stage (4) is coupled to a first input of the second stage (8), a second output (2B) of the first stage (4) being coupled to a second input of the second stage (8). A common mode feedback amplifier (12) has an input coupled to receive a common mode signal (3) from the second stage (8) for producing an amplified common mode signal (9) on a control input of the controlled active load circuit (6) to provide fast settling of an output (Vout) of the second stage without substantially increasing amplifier noise.

Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.