Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

Abstract: A superconducting switching amplifier embodying the invention includes superconductive devices responsive to input/control signals for clamping the output of the amplifier to a first voltage or to a second voltage. The amplifier includes a first set of superconducting devices serially connected between a first voltage line and an output terminal and a second set of superconducting devices serially connected between the output terminal and a second voltage line. The first set and the second set of devices are operated in a complementary fashion in response to control signals. When one of the first and second sets is driven to a superconducting (zero resistance) state the other set is driven to a resistive state. In accordance with the invention, the devices of each set are laid out in a pattern and driven in a manner to enable all the devices of each set to be driven to a selected state at substantially the same time.

Abstract: An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.

Abstract: Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

Abstract: A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith.

Abstract: A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a controllable delay element, such as, a phase rotator, for data edge tracking.

Abstract: Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.

Abstract: A pseudofooter circuit for a logic circuit includes a first FET (Field Effect Transistor) having a first source, a first drain, and a first gate, and a second FET having a second source, a second drain, and a second gate. The first source is connected to the second drain to become a first signal node. The first signal node is connected to at least one gate of an FET in the logic circuit. The first gate is connected to the second gate to become a second signal node receiving a second signal as an input signal. The second source is connected to ground. The first drain becomes a third signal node receiving a third signal as an input signal.

Abstract: Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.

Abstract: A pseudofooter circuit for a logic circuit includes a first FET (Field Effect Transistor) having a first source, a first drain, and a first gate, and a second FET having a second source, a second drain, and a second gate. The first source is connected to the second drain to become a first signal node. The first signal node is connected to at least one gate of an FET in the logic circuit. The first gate is connected to the second gate to become a second signal node receiving a second signal as an input signal. The second source is connected to ground. The first drain becomes a third signal node receiving a third signal as an input signal.

Abstract: A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith.

Abstract: Josephson transmission structures (JTSs) which include Josephson transmission lines (JTLs) with filter circuitry and flux release circuitry. Two or more of these JTSs may be interconnected to form a superconducting high-gain operational amplifier intended for general-purpose analog signal processing is disclosed. The active elements of the amplifier are non-hysteretic Josephson junctions configured as dc SQUIDs (used as flux-to voltage transducers and impedance transformers) and Josephson transmission lines (used as the main source of power gain). The amplifier has inverting and non-inverting voltage inputs, which can be fed from any low-resistance low-voltage sources, including dc SQUIDs. The output of the amplifier is in the form of a voltage which can drive typical transmission line impedances (e.g., 10-100 ohms).