Abstract: In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: Illustrative embodiments provide an apparatus for phase shifting to produce uniform phase steps in a predictable manner to improve the linearity of conversion. The apparatus comprises a phase selector for selecting two or more phases to create selected phases and a phase interpolator capable of receiving the selected phases. The apparatus further comprises a set of digital to analog converter cells connected to the phase interpolator, wherein interpolator weight distribution among the set of digital to analog converter cells is non-linear, and a thermometer code in communication with the set of digital to analog converter cells, wherein the thermometer code adjusts output of the set of digital to analog converter cells to phase shift the selected phases.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.