Patents by Inventor Sergey Y. Shishlov
Sergey Y. Shishlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10514927Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.Type: GrantFiled: March 27, 2014Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Anton Lechanka, Andrey Efimov, Sergey Y. Shishlov, Andrey Kluchnikov, Kamil Garifullin, Igor Burovenko, Boris A. Babayan
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Patent number: 10133582Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.Type: GrantFiled: December 23, 2013Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Nikolay Kosarev, Sergey Y. Shishlov, Jayesh Iyer, Alexander V. Butuzov, Boris A. Babayan, Andrey Kluchnikov
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Patent number: 10095623Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.Type: GrantFiled: October 18, 2016Date of Patent: October 9, 2018Assignee: INTEL CORPORATIONInventors: Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov, Boris A. Babayan
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Publication number: 20180285119Abstract: A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.Type: ApplicationFiled: March 27, 2015Publication date: October 4, 2018Applicant: Intel CorporationInventors: Alexandr Titov, Dmitry Maslennikov, Sergey Y. SHISHLOV, Valentin Burov, Pavel Matveyev
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Publication number: 20170235578Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.Type: ApplicationFiled: December 27, 2016Publication date: August 17, 2017Inventors: Boris A. Babayan, Vladimir M. Pentkovski, Alexander V. Butuzov, Sergey Y. Shishlov, Alexey Y. Sivtsov, Nikolay Kosarev
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Publication number: 20170161075Abstract: In an embodiment, a processor includes a plurality of cores. Each core may include strand logic to, for each strand of a plurality of strands, fetch an instruction group uniquely associated with the strand, wherein the instruction group is one of a plurality of instruction groups, wherein the plurality of instruction groups is obtained by dividing instructions of an application program according to instruction criticality. The strand logic may also be to retire the instruction group in an original order of the application program. Other embodiments are described and claimed.Type: ApplicationFiled: June 1, 2015Publication date: June 8, 2017Inventors: ALEXANDR TITOV, DMITRY M. MASLENNIKOV, SERGEY Y. SHISHLOV, SERGEY P. SCHERBININ, VALENTIN A. BUROV, RON GABOR, DENIS G. MOTIN, OLEG SHIMKO, KAMIL GARIFULLIN, ALEXANDER V. BUTUZOV, EVGENIY N. PODKORYTOV, ANDREY CHUDNOVETS
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Patent number: 9632790Abstract: A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.Type: GrantFiled: December 26, 2012Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Yuriy V Baida, Alexander V Butuzov, Bob Babayan, Vladimir Pentkovski
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Publication number: 20170039139Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: ANDREY KLUCHNIKOV, JAYESH IYER, SERGEY Y. SHISHLOV, BORIS A. BABAYAN
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Patent number: 9529596Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.Type: GrantFiled: July 1, 2011Date of Patent: December 27, 2016Assignee: Intel CorporationInventors: Boris A. Babayan, Vladimir M. Pentkovski, Alexander V. Butuzov, Sergey Y. Shishlov, Alexey Y. Sivtsov, Nikolay E. Kosarev
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Publication number: 20160364239Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.Type: ApplicationFiled: March 27, 2014Publication date: December 15, 2016Inventors: Anton Lechenko, Andrey Efimov, Sergey Y. Shishlov, Andrey Kluchnikov, Kamil Garifullin, Igor Burovenko, Boris A. Babayan
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Publication number: 20160364237Abstract: A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match the pending instructions to the execution ports based upon the program order of each pending instruction and whether each strand is active. Each pending instruction is at a respective head of one of the strands.Type: ApplicationFiled: March 27, 2014Publication date: December 15, 2016Inventors: Nikolay Kosarev, Sergey Y. Shishlov, Alexey Sivtsov, Boris A. Babayan, Alexander V. Butuzov
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Publication number: 20160314000Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.Type: ApplicationFiled: December 23, 2013Publication date: October 27, 2016Inventors: Nikolay Kosarev, Sergey Y. Shishlov, Jayesh Iyer, Alexander V. Butuzov, Boris A. Babayan, Andrey Kluchnikov
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Publication number: 20160306742Abstract: A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.Type: ApplicationFiled: December 23, 2013Publication date: October 20, 2016Inventors: Anton W. LECHENKO, Andrey EFIMOV, Sergey Y. SHISHLOV, Jayesh IYER, Boris A. BABAYAN
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Patent number: 9471501Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.Type: GrantFiled: September 26, 2014Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov, Boris A. Babayan
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Publication number: 20160092367Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov, Boris A. Babayan
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Publication number: 20150301831Abstract: A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.Type: ApplicationFiled: December 26, 2012Publication date: October 22, 2015Inventors: Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Yuriy V Baida, Alexander V Butuzov, Bob Babayan
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Publication number: 20140208074Abstract: In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2012Publication date: July 24, 2014Inventors: Boris A. Babayan, Vladimir Pentkovski, Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexander V. Butuzov, Alexey Y. Sivtsov
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Publication number: 20130007415Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Inventors: Boris A. Babayan, Vladimir M. Pentkovski, Alexander V. Butuzov, Sergey Y. Shishlov, Alexey Y. Sivtsov, Nikolay E. Kosarev