Abstract: A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

Abstract: A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.