Patents by Inventor Sergio A. Ajuria
Sergio A. Ajuria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10553508Abstract: Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.Type: GrantFiled: January 13, 2014Date of Patent: February 4, 2020Assignee: NXP USA, INC.Inventors: Douglas M. Reber, Sergio A. Ajuria, Phuc M. Nguyen
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Patent number: 10522615Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.Type: GrantFiled: December 7, 2016Date of Patent: December 31, 2019Assignee: NXP USA, INC.Inventors: Sergio A. Ajuria, Phuc M. Nguyen, Douglas M. Reber
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Publication number: 20170084682Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: SERGIO A. AJURIA, PHUC M. NGUYEN, DOUGLAS M. REBER
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Patent number: 9601354Abstract: An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.Type: GrantFiled: August 27, 2014Date of Patent: March 21, 2017Assignee: NXP USA, Inc.Inventors: Douglas M. Reber, Sergio A. Ajuria, Phuc M. Nguyen
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Patent number: 9548266Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.Type: GrantFiled: August 27, 2014Date of Patent: January 17, 2017Assignee: NXP USA, INC.Inventors: Sergio A. Ajuria, Phuc M. Nyugen, Douglas M. Reber
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Publication number: 20160064294Abstract: An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.Type: ApplicationFiled: August 27, 2014Publication date: March 3, 2016Inventors: DOUGLAS M. REBER, Sergio A. Ajuria, Phuc M. Nguyen
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Publication number: 20160064324Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.Type: ApplicationFiled: August 27, 2014Publication date: March 3, 2016Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Sergio A. Ajuria, Phuc M. Nyugen, Douglas M. Reber
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Patent number: 9134366Abstract: A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.Type: GrantFiled: August 27, 2013Date of Patent: September 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Sergio A. Ajuria, Phuc M. Nguyen, Douglas M. Reber
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Publication number: 20150200146Abstract: Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Inventors: Douglas M. Reber, Sergio A. Ajuria, Phuc M. Nguyen
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Publication number: 20150061709Abstract: A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Inventors: Sergio A. Ajuria, Phuc M. Nguyen, Douglas M. Reber
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Patent number: 8059380Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.Type: GrantFiled: May 15, 2008Date of Patent: November 15, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Sergio A. Ajuria, Melanie Etherton, Marc A. Mangrum
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Publication number: 20090284881Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Inventors: Sergio A. Ajuria, Melanie Etherton, Marc A. Mangrum
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Patent number: 5963818Abstract: A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench region (208a) and a damascene gate electrode (214) using a common dielectric layer (208), MOS integrated circuits can be formed with reduced processing steps while simultaneously avoiding adverse polysilicon stringers which are present in prior art damacene-formed gate electrode. A single dielectric layer (208) is deposited in order to provide trench fill material for a trench region (208a) while simultaneously providing the material needed for form an opening (210) which is used to define the dimensions and material content of a gate electrode (214).Type: GrantFiled: September 17, 1997Date of Patent: October 5, 1999Assignee: Motorola, IncInventors: Soolin Kao, Sergio A. Ajuria, Diann M. Dow, Susan E. Soggs
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Patent number: 5885870Abstract: In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.Type: GrantFiled: July 2, 1997Date of Patent: March 23, 1999Assignee: Motorola, Inc.Inventors: Bikas Maiti, Philip J. Tobin, Sergio A. Ajuria
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Patent number: 5665620Abstract: A stack of oxide (16) and silicon nitride (18) is grown/deposited over a patterned polysilicon line, which typically acts as a bottom capacitor plate. A thin layer of amorphous or polycrystalline silicon (20) is deposited over the blanket silicon nitride film. The thickness of the deposited silicon layer must be optimized according to the final amount of oxide desired over the silicon nitride, which will be roughly twice the thickness of the deposited silicon film. The oxide/nitride/silicon stack is then patterned and etched, stopping either at or underneath the bottom oxide. Any subsequent cleaning in potentially oxide-etching chemistries (including HF) is done with the protective silicon deposit on top of the silicon nitride. The entire structure is then thermally oxidized, transforming the deposited silicon into silicon oxide (30). Where the structure has been cleared down to the substrate by etching, a second gate oxide is simultaneously formed.Type: GrantFiled: August 1, 1994Date of Patent: September 9, 1997Assignee: Motorola, Inc.Inventors: Bich-Yen Nguyen, Sergio A. Ajuria, Wayne Paulson, Jon Dahm
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Patent number: 5510645Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.Type: GrantFiled: January 17, 1995Date of Patent: April 23, 1996Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Papu Maniar, Keith E. Witek, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria
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Patent number: 5324683Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.Type: GrantFiled: June 2, 1993Date of Patent: June 28, 1994Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Papu Maniar, Keith E. Witek, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria