Abstract: A charge pump configured for use in a phase-locked loop includes positive and negative current sources, transistor switches, voltage nodes and one or more operational amplifiers, wherein the positive and negative current sources each includes an output node, the output nodes are respectively connected sequentially to the voltage nodes having substantially the same voltage, the transistor switches are configured to sequentially switch such that at all times there is one transistor switch connection, and the currents flows through the transistor switches into one of the voltage nodes. One of the voltage nodes is connected to the PLL filter and the transistor switches are connected to the PLL filter and are controlled by the phase error pulses. Two voltage nodes are possible. The second node provides feedback. The currents to the second node are supplied substantially simultaneously for the same amount of time.

Abstract: An apparatus for reducing undesirable low-frequency distortion in a direct conversion communication receiver includes a signal generator to produce a first periodic signal and a second periodic signal. A merge circuit combines an input signal and the first periodic signal to produce a modulated signal with a polarity switched component. A frequency translation circuit converts the modulated signal into a baseband signal with a spectrum substantially equal to the modulated signal, but centered around a carrier frequency of approximately zero and including a low-frequency error component. An output modulator circuit combines the baseband signal with the second periodic signal to produce a modified baseband signal wherein the low-frequency error component is shifted to a high frequency spectrum position and the polarity switched component is eliminated.

Abstract: A multi-level quadrature (I/Q) mixer for use in a communication system such as a paging device, where the mixer includes first and second I/Q downconversions followed by demodulation. The first I/Q downconversion converts an I/Q signal pair to a first IF, and the second I/Q downconversion converts an I/Q signal pair to a second IF. The first IF may or may not be the center frequency depending on the number of subchannels in the single channel being downconverted.

Abstract: A demodulation circuit providing for detection of multiple zero-crossings in an FSK signal. High data rate signals are demodulated by generating, for each pair of baseband signals I and Q, additional I and Q pairs which are phase shifted from the original I and Q pair. By generating zero crossing signals for the original baseband signals and for the phase shifted signals, additional zero crossings may be detected allowing demodulation of relatively high data rate modulated signals.

Abstract: Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.

Abstract: A sample-and-hold circuit for sampling a time-varying signal comprises a main sample-and-hold subcircuit extending between input and output terminals and an auxiliary sample-and-hold subcircuit extending between the input terminal and a portion of the main subcircuit. Each sample-and-hold subcircuit comprises an input buffer amplifier, a diode-bridge switch responsive to a control signal and coupled to the input buffer amplifier, a charge-holding capacitor coupled to the switch, and an output buffer amplifier coupled to the capacitor. The output of the auxiliary output amplifier is further coupled to the main switch and the output of the main output amplifier is coupled to the output terminal. A generator generates the control signal for controlling the switches such that the same part of the time-varying signal passing through the main and auxiliary subcircuits is sampled.

Abstract: A sample and hold circuit made entirely of NPN transistors, capacitors and resistors uses double emitter-follower transistors for gating an input signal onto a charging capacitor. A transistor connected in parallel to the first of the emitter-follower transistors is controlled to conduct blow-by current away from the second emitter-follower transistor in the hold state. A step voltage is applied to the charge capacitor in the hold state to prevent turn on of the emitter-follower transistors. The circuit is configured with complementary components so that a differential output signal eliminating the step voltage is provided.