Patents by Inventor Sergio ABENDA

Sergio ABENDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803226
    Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 31, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta′, Sergio Abenda
  • Publication number: 20210357015
    Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta', Sergio Abenda
  • Patent number: 11144678
    Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 12, 2021
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda, Layachi Daineche
  • Patent number: 10891399
    Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics S.R.L.
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda
  • Publication number: 20180341791
    Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
    Type: Application
    Filed: April 4, 2018
    Publication date: November 29, 2018
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda
  • Publication number: 20180260585
    Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Inventors: Mirko DONDINI, Gaetano DI STEFANO, Sergio ABENDA, Layachi DAINECHE