Abstract: An integrated circuit die (10) includes a substrate (64), a plurality of metal interconnect layers (62) formed over the substrate (64), an insulating layer (58), a first pad (12), a second pad (14), and a probe pad (16). The first pad (12) is formed over the insulating layer (58) at an edge (11) of the integrated circuit die (10). The second pad (14) is formed over the insulating layer (58) adjacent to the first pad (12) on a side of the first pad (12) that is opposite to the edge (11). The probe pad (16) is formed over the insulating layer (58) on a side of the second pad (14) that is opposite to the edge (11), wherein the probe pad (16) is electrically connected to the first pad (12). The probe pad (16) may be formed over active circuitry of the substrate instead of over a peripheral area of the die (10), thus reducing the surface area of the die (10).

Abstract: A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).

Abstract: A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).