Abstract: Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Abstract: Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Abstract: A method and circuit are described for improving the pointer processing in the case of synchronous digital hierarchy (SDH) or synchronous optical network (SONET) transmission frames with VC4_4c, VC4_16c and VC4_64c concatenated payloads. The technique proposed by the existing Standards provides for two different state diagrams to be used in the pointer processing algorithm. One state diagram is used in the case of a concatenated payload and the other state diagram is used in the case of a non-concatenated payload. However, no solution is disclosed for automatically going from the states of one diagram to the states of the other diagram. The present invention provides a circuit so constructed that it can be used in an apparatus processing STM-4, STM-16 and STM-64 frames, through which the automatic recognition of the VC4-4c, VC4-16c and VC4-64c payload concatenation can be achieved. Therefore, it is not necessary to configure in advance the concatenation or non-concatenation condition.