Abstract: The disclosed embodiments provide a system that operates a processor in a computer system. During operation, the system uses the processor to maintain a count of outstanding input/output (I/O) requests for a component in the computer system. Next, the system facilitates efficient execution of the processor by overriding a latency tolerance reporting (LTR) value for the component based on the count.

Abstract: A composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics, is described. This composite memory device may receive requests, a given one of which includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command. For the given request, the composite memory device executes the command on the block of data at the logical address in at least one of the types of non-volatile memory devices. Furthermore, the composite memory device conditionally executes the hint based on one or more criteria, such as: available memory in the types of non-volatile memory devices, traffic through an interface circuit in the composite memory device, operational states of the types of non-volatile memory devices, a target performance characteristic of the composite memory device, and an environmental condition of the composite memory device.

Abstract: The disclosed embodiments provide a system that facilitates the processing of commands in a set of devices. The system includes a host bus adapter that provides an interface for connecting the set of devices to the host and manages the allocation of a set of tags to one or more of the devices. For each device connected to the host, the system also includes a queue-management apparatus that sends a tag request for the device to the host bus adapter. The queue-management apparatus then receives a subset of the tags for the device from the host bus adapter and uses the set of tags to queue commands from the host to the device and track the status of the queued commands.

Abstract: The disclosed embodiments provide a system that operates a processor in a computer system. During operation, the system uses the processor to maintain a count of outstanding input/output (I/O) requests for a component in the computer system. Next, the system facilitates efficient execution of the processor by overriding a latency tolerance reporting (LTR) value for the component based on the count.

Abstract: The disclosed embodiments provide a system that facilitates the processing of commands in a set of devices. The system includes a host bus adapter that provides an interface for connecting the set of devices to the host and manages the allocation of a set of tags to one or more of the devices. For each device connected to the host, the system also includes a queue-management apparatus that sends a tag request for the device to the host bus adapter. The queue-management apparatus then receives a subset of the tags for the device from the host bus adapter and uses the set of tags to queue commands from the host to the device and track the status of the queued commands.

Abstract: The disclosed embodiments provide a system that facilitates the processing of commands in a set of devices. The system includes a host bus adapter that provides an interface for connecting the set of devices to the host and manages the allocation of a set of tags to one or more of the devices. For each device connected to the host, the system also includes a queue-management apparatus that sends a tag request for the device to the host bus adapter. The queue-management apparatus then receives a subset of the tags for the device from the host bus adapter and uses the set of tags to queue commands from the host to the device and track the status of the queued commands.

Abstract: The disclosed embodiments provide a system that facilitates the processing of commands in a set of devices. The system includes a host bus adapter that provides an interface for connecting the set of devices to the host and manages the allocation of a set of tags to one or more of the devices. For each device connected to the host, the system also includes a queue-management apparatus that sends a tag request for the device to the host bus adapter. The queue-management apparatus then receives a subset of the tags for the device from the host bus adapter and uses the set of tags to queue commands from the host to the device and track the status of the queued commands.

Abstract: A composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics, is described. This composite memory device may receive requests, a given one of which includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command. For the given request, the composite memory device executes the command on the block of data at the logical address in at least one of the types of non-volatile memory devices. Furthermore, the composite memory device conditionally executes the hint based on one or more criteria, such as: available memory in the types of non-volatile memory devices, traffic through an interface circuit in the composite memory device, operational states of the types of non-volatile memory devices, a target performance characteristic of the composite memory device, and an environmental condition of the composite memory device.