Abstract: An apparatus may include a system including a plurality of integrated circuits (ICs), including a first IC having a first set of agent circuits and a second IC having a second set of agent circuits. The first IC may include a first interface with a first always-on portion and a first power-managed portion. The second IC may include a second interface coupled to the first interface, and having a second always-on portion and a second power-managed portion. A first agent circuit of the first set of agent circuits in the first IC may be configured to send, while the second IC is in a reduced power state, a transaction to a second agent circuit. The first interface may be configured to communicate, via the always-on portions of the first and second interfaces, with the second IC to cause the second IC to wake up the second agent circuit.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

Abstract: Techniques are disclosed related to a scalable system on a chip (SOC). In some embodiments, a system includes a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers configured to support scaling of the system using a unified memory architecture.

Abstract: An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

Abstract: An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: Techniques are disclosed pertaining to utilizing a communication fabric via multiple ports. An agent circuit includes a plurality of command-and-data ports that couple the agent circuit to a communication fabric coupled to a plurality of hardware components that includes a plurality of memory controller circuits that facilitate access to a memory. The agent circuit can execute an instruction that involves issuing a command for data stored at the memory. The agent circuit may perform a hash operation on a memory address associated with the command to determine which one of the plurality of memory controller circuits to which to issue the command. The agent circuit issues the command to the determined memory controller circuit on a particular one of the plurality of command-and-data ports that is designated to the memory controller circuit. The agent circuit may issue all commands destined to that memory controller circuit on that port.

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to a plurality of networks of the computer system, which may include packet-switching capabilities. Such non-DRAM transactions may be routed via a virtual channel in some implementations. To facilitate handling of such transactions, the NSM gateway circuit may include dedicated routing storage (e.g., an input buffer for each source agent circuit on each of the plurality of networks and an output buffer for each destination agent circuit on each of the plurality of networks). The NSM gateway circuit may serve as a termination point for non-DRAM transactions within the computer system, allowing network credit for a message included in a non-DRAM transaction to be returned to a source agent circuit prior to delivery to one or more destination agent circuits.

Abstract: An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to first and second networks of the computer system. The NSM gateway circuit may route, for example, a message for a non-DRAM transaction from a source agent circuit coupled to the first network but not the second network to a destination agent circuit coupled to the second network but not the first network, and vice-versa. The NSM gateway circuit can also route messages for non-DRAM transactions between source and destination agent circuits both located on the same network. Still further, the NSM gateway circuit can route broadcast (i.e., one-to-many) transactions as well as network element configuration requests. In some implementations, a computer system may have multiple NSM gateway circuits, each assigned to handle non-DRAM transactions from an assigned set of agent circuits.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.