Patents by Inventor Sergio Moretti

Sergio Moretti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5222655
    Abstract: An apparatus for applying a soldering alloy to an element to be soldered including an open-channeled member having a receiving region for holding the element, a vacuum system connected to the member for creating a negative pressure through the open channel and at the receiving region sufficient to retain the element against the receiving region, a heating coil connected to the member for conducting heat to the element at a soldering temperature, and a gas distribution and heating system for providing heated gas to a soldering alloy at a temperature sufficient to melt and provide at least one soldering connection on the heated element. The invention also comprises a method for providing heat to an element to be soldered substantially by conduction and heat to a soldering alloy substantially by convection employing a heated gas all at temperatures sufficient to provide a soldered connection without damaging the element being soldered.
    Type: Grant
    Filed: March 28, 1991
    Date of Patent: June 29, 1993
    Assignee: Selenia Industrie Elettroniche Associate
    Inventors: Sergio Moretti, Ugo Fracassi
  • Patent number: 5130764
    Abstract: A technique utilizing conventional photolithography to manufacture GaAs MESFET devices having sub-micrometric gate and variable length recessed channel. The structure of these devices consists of two photopolymeric layers separated by a metal interface. The upper, stencil layer sets the aperture of the submicrometric gate. The lower planarizing layer defines the recessed channel, through the metal interface, which acts as a template. The length of such channel may be varied through suitable choice of exposure time of the planarizing photopolymer. By adopting such multilayer structures it is possible to obtain gate lengths of .about.b .mu.m and recessed channel lengths form 0.8 to 3 .mu.m, with a process yield typically better than 90%, simultaneously. Furthermore, by using a thicker planarizing layer in this structure it is possible to obtain a relatively thick metal deposit (typically about 0.8 .mu.m), such as a Ti/Pt/Au overlayer over ohmic contacts and gate pads.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: July 14, 1992
    Assignee: Selenia Industrie Elettroniche Associate
    Inventors: Antonio Cetronio, Sergio Moretti, Vittoria Compagnucci
  • Patent number: 4818724
    Abstract: A method of making semiconductive developments, especially MESFETs, which applies a template to a surface of the substrate previously formed with circuit elements in alignment with these elements and so bonds the template to the substrate that the template can be utilized as a holder for the substrate. The rear surface is then coated with a resist and a second template aligned externally with the first utilizing markings exterior to the substrate to form the structure on the rear surface which can include throughholes for a metal deposit extending through the preferably GaAs substrate.
    Type: Grant
    Filed: June 30, 1987
    Date of Patent: April 4, 1989
    Assignee: Selenia Industrie Elettroniche Associate S.P.A.
    Inventors: Antonio Cetronio, Sergio Moretti, Maurizio Di Bona