Patents by Inventor Sergio P. Pacheco

Sergio P. Pacheco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9362234
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Eduard J. Pabst, Sergio P. Pacheco, Weng F. Yap
  • Publication number: 20150194388
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 9, 2015
    Inventors: EDUARD J. PABST, SERGIO P. PACHECO, WENG F. YAP
  • Patent number: 7439606
    Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 21, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lianjun Liu, Qiang Li, Melvy F. Miller, Sergio P. Pacheco
  • Patent number: 7276420
    Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: October 2, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lianjun Liu, Qiang Li, Melvy F. Miller, Sergio P. Pacheco