Abstract: A peripheral device connecting system with priority arbitration includes a connection matrix connected to a plurality of peripheral devices capable of transmitting a signal to be arbitrated, e.g., an interrupt enable signal. The connection matrix includes first and second connection matrices connected to each other through a plurality of logic gates having a progressive number of inputs for transmitting in parallel a plurality of signals to be arbitrated. A connection matrix for a microcontroller-emulating chip includes a peripheral device connecting system with priority arbitration.

Abstract: The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA