Patents by Inventor Sergio Reyes
Sergio Reyes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230121058Abstract: A system and a method to expedite a response of a risk engine to novel threats by detecting an anomalous amount of outlier requests and making more conservative identity assurance assessments during a time period it takes to identify and properly respond to the novel threat. Here, in detecting the novel threats, the response of the risk engine is temporarily altered until the novel threats have subsided or are no longer novel.Type: ApplicationFiled: October 17, 2022Publication date: April 20, 2023Applicant: TLA Innovation, Inc.Inventors: Kala KINYON, Sergio REYES, Ricardo GONZALEZ, Jeremy CORBELLO
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Patent number: 11593004Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.Type: GrantFiled: August 13, 2021Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Sergio Reyes, Brian Chase Twichell
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Publication number: 20230051684Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Sergio Reyes, Brian Chase Twichell
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Publication number: 20220318337Abstract: An approach for classifying ordered data. The approach can calculate a cumulative sum (CUSUM) chart for an ordered dataset and determine a peak and valley for the CUSUM chart. The approach can plot three rays, a first ray between the beginning of the CUSUM chart and the peak/valley, a second ray between select the peak/valley and the peak/valley and a third ray between the peak/valley and the end of the CUSUM chart. The approach can calculate three angles formed by the three rays and an x-axis associated with the CUSUM chart. It should be noted that the sign of the angle matches the sign of the slope of the ray. The approach can translate the three angles to three symbols based on a translation table associated with an ordered character set and generate a classification based on concatenating the three symbols.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Sergio Reyes, Samuel Kipling Ingram, Brian Chase Twichell, Yijie Zhang
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Patent number: 10915355Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.Type: GrantFiled: April 9, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Patent number: 10788991Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.Type: GrantFiled: March 23, 2018Date of Patent: September 29, 2020Assignee: International Business Machines CorporationInventors: Sergio Reyes, Brian C. Twichell
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Patent number: 10776143Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.Type: GrantFiled: June 17, 2014Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
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Patent number: 10740127Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.Type: GrantFiled: September 19, 2014Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
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Patent number: 10481823Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.Type: GrantFiled: February 21, 2018Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
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Publication number: 20190258421Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.Type: ApplicationFiled: February 21, 2018Publication date: August 22, 2019Inventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
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Publication number: 20190235914Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.Type: ApplicationFiled: April 9, 2019Publication date: August 1, 2019Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Patent number: 10261799Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.Type: GrantFiled: February 28, 2017Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Patent number: 10241688Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.Type: GrantFiled: March 9, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Publication number: 20180260143Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.Type: ApplicationFiled: March 9, 2017Publication date: September 13, 2018Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Publication number: 20180260144Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.Type: ApplicationFiled: September 25, 2017Publication date: September 13, 2018Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Publication number: 20180246726Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
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Publication number: 20180210662Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.Type: ApplicationFiled: March 23, 2018Publication date: July 26, 2018Inventors: Sergio Reyes, Brian C. Twichell
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Patent number: 10019175Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: August 31, 2016Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Sergio Reyes, Brian C. Twichell
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Publication number: 20180059957Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Sergio Reyes, Brian C. Twichell
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Patent number: 9250947Abstract: A technique for determining placement fitness for partitions under a hypervisor in a host computing system having non-uniform memory access (NUMA) nodes. In an embodiment, a partition resource specification is received from a partition score requester. The partition resource specification identifies a set of computing resources needed for a virtual machine partition to be created by a hypervisor in the host computing system. Resource availability within the NUMA nodes of the host computing system is assessed to determine possible partition placement options. A partition fitness score of a most suitable one of the partition placement options is calculated. The partition fitness score is reported to the partition score requester.Type: GrantFiled: July 14, 2015Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Richard Mankowski, Bret R. Olszewski, Sergio Reyes