Patents by Inventor Sergio Reyes

Sergio Reyes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230121058
    Abstract: A system and a method to expedite a response of a risk engine to novel threats by detecting an anomalous amount of outlier requests and making more conservative identity assurance assessments during a time period it takes to identify and properly respond to the novel threat. Here, in detecting the novel threats, the response of the risk engine is temporarily altered until the novel threats have subsided or are no longer novel.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 20, 2023
    Applicant: TLA Innovation, Inc.
    Inventors: Kala KINYON, Sergio REYES, Ricardo GONZALEZ, Jeremy CORBELLO
  • Patent number: 11593004
    Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian Chase Twichell
  • Publication number: 20230051684
    Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Sergio Reyes, Brian Chase Twichell
  • Publication number: 20220318337
    Abstract: An approach for classifying ordered data. The approach can calculate a cumulative sum (CUSUM) chart for an ordered dataset and determine a peak and valley for the CUSUM chart. The approach can plot three rays, a first ray between the beginning of the CUSUM chart and the peak/valley, a second ray between select the peak/valley and the peak/valley and a third ray between the peak/valley and the end of the CUSUM chart. The approach can calculate three angles formed by the three rays and an x-axis associated with the CUSUM chart. It should be noted that the sign of the angle matches the sign of the slope of the ray. The approach can translate the three angles to three symbols based on a translation table associated with an ordered character set and generate a classification based on concatenating the three symbols.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Sergio Reyes, Samuel Kipling Ingram, Brian Chase Twichell, Yijie Zhang
  • Patent number: 10915355
    Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Patent number: 10788991
    Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 10776143
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10740127
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10481823
    Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
  • Publication number: 20190258421
    Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 22, 2019
    Inventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
  • Publication number: 20190235914
    Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Patent number: 10261799
    Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Patent number: 10241688
    Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Publication number: 20180260143
    Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 13, 2018
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Publication number: 20180260144
    Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.
    Type: Application
    Filed: September 25, 2017
    Publication date: September 13, 2018
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Publication number: 20180246726
    Abstract: A mechanism is provided for programmatic implicit multithreading. A first operation is executed on a first thread in a processor, where the first operation is from a set of operations within a block of code of an application that are distinct and process unrelated data. A determination is made as to whether a time limit associated with executing the first operation has been exceeded. Responsive to the time limit being exceeded, a determination is made as to whether there is one or more unexecuted operations in the set of operations. Responsive to one or more unexecuted operations existing in the set of operations, a new thread is spawned off on the processor to execute a next unexecuted operation of the one or more unexecuted operations.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Inventors: Samuel K. Ingram, Sergio Reyes, Brian C. Twichell, Yijie Zhang
  • Publication number: 20180210662
    Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 10019175
    Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell
  • Publication number: 20180059957
    Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 9250947
    Abstract: A technique for determining placement fitness for partitions under a hypervisor in a host computing system having non-uniform memory access (NUMA) nodes. In an embodiment, a partition resource specification is received from a partition score requester. The partition resource specification identifies a set of computing resources needed for a virtual machine partition to be created by a hypervisor in the host computing system. Resource availability within the NUMA nodes of the host computing system is assessed to determine possible partition placement options. A partition fitness score of a most suitable one of the partition placement options is calculated. The partition fitness score is reported to the partition score requester.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Richard Mankowski, Bret R. Olszewski, Sergio Reyes