Abstract: Systems, methods, and devices are described herein for a word line interlock circuit. A device includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate is configured to receive a reset signal. The interlock circuit is coupled to an output of the first logic gate and is configured to generate a first signal and selectively operate the first logic gate. The delay circuit is coupled to an output of the interlock circuit and is configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit. In response to the reset signal changing logic states, the selective operation of the first logic gate prevents changing edges of the reset signal from being transmitted to the delay circuit.

Abstract: A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.

Abstract: A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.

Abstract: In a method, error detection and correction is performed on output data from a memory cell of a memory device to generate a result of error detection and correction. The memory cell is determined as a weak cell by determining a number of times of data retention failures of the memory cell based on the result of the error detection and correction. In a refreshing cycle, normal cells and the weak cell are refreshed and the weak cell is additionally refreshed at least once.

Abstract: A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval.

Abstract: Apparatuses and devices are provided for bias level correction. An example apparatus includes: a bias-voltage generator configured to generate a bias voltage; a first transmission component configured to receive the bias voltage and generate a first output signal based at least in part on the bias voltage and one or more first data signals; and a first bias-level correction component configured to generate one or more first pulses based at least in part on the one or more first data signals to suppress one or more ripples associated with the bias voltage.

Abstract: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments.

Abstract: Apparatuses and devices are provided for bias level correction. An example apparatus includes: a bias-voltage generator configured to generate a bias voltage; a first transmission component configured to receive the bias voltage and generate a first output signal based at least in part on the bias voltage and one or more first data signals; and a first bias-level correction component configured to generate one or more first pulses based at least in part on the one or more first data signals to suppress one or more ripples associated with the bias voltage.

Abstract: A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A magnetoresistive random access memory (MRAM) bit cell includes a first magnetic tunnel junction (MTJ) connected to a first data line. The MRAM bit cell further includes a second MTJ connected to a second data line. The MRAM bit cell further includes a pass gate assembly connected to the first MTJ and the second MTJ, wherein the pass gate assembly comprises a plurality of transistors, and each transistor of the plurality of transistors is configured to selectively connect the first MTJ and the second MTJ to a driving line.

Abstract: A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier in a first mode, and couple a cell of the cell segment to the first node of the current sense amplifier, and couple the first and second reference cells to the second node of the current sense amplifier in a second mode.

Abstract: A magnetoresistive random access memory (MRAM) bit cell includes a first magnetic tunnel junction (MTJ) connected to a first data line. The MRAM bit cell further includes a second MTJ connected to a second data line. The MRAM bit cell further includes a pass gate assembly connected to the first MTJ and the second MTJ, wherein the pass gate assembly comprises a plurality of transistors, and each transistor of the plurality of transistors is configured to selectively connect the first MTJ and the second MTJ to a driving line.

Abstract: A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier in a first mode, and couple a cell of the cell segment to the first node of the current sense amplifier, and couple the first and second reference cells to the second node of the current sense amplifier in a second mode.

Abstract: A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal.

Abstract: A MRAM bit cell including a first magnetic tunnel junction (MTJ) connected to a first data line and a second MTJ connected to a second data line. The MRAM bit cell further includes a first transistor having a first terminal connected to the first MTJ and a second terminal connected to the second MTJ. The MRAM bit cell further includes a second transistor having a first terminal connected to a driving line and a second terminal connected to the first MTJ. The MRAM bit cell further includes a third transistor having a first terminal connected to the driving line and a second terminal connected to the second MTJ. A method of using the MRAM bit cell is also described.

Abstract: In a method for boosting a word line signal, the word line signal is transitioned from a first voltage value of the word line signal to a second voltage value of the word line signal, thereby turning on a first transistor. The first transistor and a second transistor turn on a third transistor. The third transistor causes the word line signal at a first terminal of the third transistor to reach a voltage value at a second terminal of the third transistor, thereby causing the word line signal to reach the voltage value faster than without the third transistor. The first transistor and the second transistor are coupled in series.

Abstract: A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with a first node and a second node for currents therethrough to be compared with each other. A cell of the first cell segment and a cell of the second cell segment are coupled to the first nodes of the first and second current sense amplifiers, respectively, and the first and second reference cells are coupled to both the second nodes of the first and second current sense amplifiers.