Abstract: Systems and methods to measure signal propagation delay through objects. The system includes a controller, a single shot pulse generator, a first pulse/edge former, a multiplexer/demultiplexer, a second pulse/edge former, a timer, and a counter. The controller initializes the system, the clock and the counter. A pulse is sent from the single shot pulse generator to the first pulse/edge former. The pulse is propagated through the first pulse/edge former to the multiplexer, through a device under test, to the demultiplexer, and to the second pulse/edge former. The second pulse edge generator provides the pulse to the counter, which counts a predetermined number of pulses, and the clock, which measures the amount of time the counter counts the pulses. The propagation delay of the device under test is then calculated based on the counted number of pulses and the elapsed time measured by the clock.

Abstract: One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.

Abstract: Systems and methods to measure signal propagation delay through objects. The system includes a controller, a single shot pulse generator, a first pulse/edge former, a multiplexer/demultiplexer, a second pulse/edge former, a timer, and a counter. The controller initializes the system, the clock and the counter. A pulse is sent from the single shot pulse generator to the first pulse/edge former. The pulse is propagated through the first pulse/edge former to the multiplexer, through a device under test, to the demultiplexer, and to the second pulse/edge former. The second pulse edge generator provides the pulse to the counter, which counts a predetermined number of pulses, and the clock, which measures the amount of time the counter counts the pulses. The propagation delay of the device under test is then calculated based on the counted number of pulses and the elapsed time measured by the clock.

Abstract: Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The first bit sequence is transmitted through an optoelectronic device and compared with corresponding bit groups in the second bit sequence. The optoelectronic device is disabled and a count of compared bit groups is kept until the comparison indicates that the optoelectronic device is completely off. Using the count and one or more of the bit groups, a turn-off time is calculated. Alternatively, the method is used to calculate a turn-on time. The optoelectronic device is enabled and a count is kept from the time the device is enabled to when the comparison of the corresponding bit groups indicates that the optoelectronic device is completely on.

Abstract: One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to measure a signal propagation delay through an object connected to an optoelectronic device. The present invention includes determining for how long after a specific bit or bit group is transmitted by an optical transceiver the bit or bit group is received at the other end of the object connected to the optical transceiver.

Abstract: A system and method for testing the jitter tolerance and signal attenuation tolerance of an optoelectronic device is disclosed. The system includes a generation circuit, delay circuit and comparison circuitry. A first sequence of bits is generated, delayed, and sent to the optoelectronic device. The optoelectronic device receives the bits and retransmits them as a second sequence to the comparison circuitry, which compares the two bit sequences to determine a bit error rate. The bit error rate is then used to determine the jitter tolerance and, in an alternate embodiment, the signal attenuation tolerance of the optoelectronic device being tested.

Abstract: Systems and methods for testing bit processing capacities of electronic devices and for reducing or eliminating jitter that compromises the ability of electronic devices to perform this task. Embodiments include circuitry and a methodology for locating and employing a data signal delay—in conjunction with a latch—to reduce or eliminate jitter from serial encoded data generated by a serializer/deserializer. The data signal delay ensures that the latch latches a state of the serial encoded data at a position within a data signal cycle of minimum jitter.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.

Abstract: A system and method for testing the jitter tolerance and signal attenuation tolerance of an optoelectronic device is disclosed. The system includes a generation circuit, delay circuit and comparison circuitry. A first sequence of bits is generated, delayed, and sent to the optoelectronic device. The optoelectronic device receives the bits and retransmits them as a second sequence to the comparison circuitry, which compares the two bit sequences to determine a bit error rate. The bit error rate is then used to determine the jitter tolerance and, in an alternate embodiment, the signal attenuation tolerance of the optoelectronic device being tested.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to measure a signal propagation delay through an object connected to an optoelectronic device. The present invention includes determining for how long after a specific bit or bit group is transmitted by an optical transceiver the bit or bit group is received at the other end of the object connected to the optical transceiver.

Abstract: Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The first bit sequence is transmitted through an optoelectronic device and compared with corresponding bit groups in the second bit sequence. The optoelectronic device is disabled and a count of compared bit groups is kept until the comparison indicates that the optoelectronic device is completely off. Using the count and one or more of the bit groups, a turn-off time is calculated. Alternatively, the method is used to calculate a turn-on time. The optoelectronic device is enabled and a count is kept from the time the device is enabled to when the comparison of the corresponding bit groups indicates that the optoelectronic device is completely on.