Abstract: A system for controlling a motor with a plurality of motor control functions including at least a current control loop and a velocity control loop. The system includes one of a hybrid Digital Signal Processor (DSP)-Field Programmable Gate Array (FPGA) architecture having an integral DSP and an integral FPGA or a System on a Chip (SoC) architecture having a Microcontroller Sub-System (MSS) and an FPGA fabric. The current control loop function is assigned to the integral FPGA for the hybrid DSP-FPGA architecture, and at least the velocity control loop function is assigned to the DSP the hybrid DSP-FPGA architecture. Alternatively, the current control loop function is assigned the FPGA fabric of the SoC architecture, and at least the velocity control loop function is assigned to the MSS of the SoC architecture.

Abstract: A resolver interface system for a motor drive system includes a phase detector configured to be operatively connected to a rotation signal output of a resolver to receive a rotation signal therefrom and generate a phase difference signal. A differentiator is operatively connected to an output of the phase detector to convert the phase difference signal of the phase detector into a pulse output configured to be read by a processing system.

Abstract: A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.

Abstract: A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.

Abstract: A system for controlling a motor with a plurality of motor control functions including at least a current control loop and a velocity control loop. The system includes one of a hybrid Digital Signal Processor (DSP)-Field Programmable Gate Array (FPGA) architecture having an integral DSP and an integral FPGA or a System on a Chip (SoC) architecture having a Microcontroller Sub-System (MSS) and an FPGA fabric. The current control loop function is assigned to the integral FPGA for the hybrid DSP-FPGA architecture, and at least the velocity control loop function is assigned to the DSP the hybrid DSP-FPGA architecture. Alternatively, the current control loop function is assigned the FPGA fabric of the SoC architecture, and at least the velocity control loop function is assigned to the MSS of the SoC architecture.

Abstract: Embodiments of the invention include methods, systems and devices for implementing the auto detection of Joint Test Action Group (JTAG) debuggers/emulators. Embodiments include sending a reset signal to reset one or more slave devices, and detecting a programming signal indicating the one or more slave devices are in a programming/debugging mode. Embodiments also include responsive to the signal, inhibiting resetting one or more slave devices receiving the programming signal.

Abstract: Aspects include a hold-up capacitor charging circuit for a power supply. The hold-up capacitor charging circuit includes a voltage boosting charge pump circuit with a hold-up capacitor electrically coupled to a voltage source. The hold-up capacitor charging circuit also includes a fly-back circuit. The fly-back circuit includes a transformer with a primary winding electrically coupled to the voltage source and a secondary winding electrically coupled to a load. A switch is electrically coupled to the primary winding and the voltage boosting charge pump circuit. A controller is operable to open and close the switch to control energy transfer from the primary winding to the secondary winding and charge the hold-up capacitor responsive to voltages of the voltage source, the voltage boosting charge pump circuit, and a reflected voltage of the secondary winding at the primary winding.

Abstract: In accordance with one or more embodiments, a monostable multivibrator that is communicatively coupled to a host device and an external analog-to-digital converter is provided. The monostable multivibrator receives a chip select signal from the host device. The monostable multivibrator also generates, in response to the chip select signal, a conversion start signal to the external analog-to-digital converter.

Abstract: In accordance with one or more embodiments, a monostable multivibrator that is communicatively coupled to a host device and an external analog-to-digital converter is provided. The monostable multivibrator receives a chip select signal from the host device. The monostable multivibrator also generates, in response to the chip select signal, a conversion start signal to the external analog-to-digital converter.