Patents by Inventor Sesh Ramaswami

Sesh Ramaswami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140273354
    Abstract: A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Sesh RAMASWAMI, Chin Hock TOH, Niranjan KUMAR
  • Patent number: 8329575
    Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 11, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • Patent number: 8283237
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • Publication number: 20120164829
    Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • Publication number: 20120164827
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Ji Ae PARK, Ryan YAMASE, Shamik PATEL, Thomas NOWAK, Li-Qun XIA, Bok Hoen KIM, Ran DING, Jim BALDINO, Mehul NAIK, Sesh RAMASWAMI
  • Patent number: 7294242
    Abstract: An apparatus and method for sputter depositing a magnetic film on a substrate to produce a magnetic device such as magnetic recording heads for reading digital information from a storage medium. The apparatus of the invention includes a sputtering chamber containing a target and a substrate, and a magnet array disposed within the chamber to form a substantially parallel magnetic field at a surface of the substrate. The sputtering chamber reduces interference between the magnetron and the magnet array by providing a long throw distance and/or a grounded collimator. The magnet array is preferably a circular ring.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: November 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Imran Hashim, Seh-Kwang Lee, Thomas Brezoczky, Sesh Ramaswami
  • Publication number: 20020119657
    Abstract: The present invention provides a method for improving the adhesion of copper and other metal-comprising conductive metals to a barrier layer. A barrier is provided that has a first surface that is substantially unoxidized, wherein at least a portion of the surface is free from the presence of oxygen atoms. A conductive layer is then deposited onto the first surface of the barrier layer. The substantially unoxidized state of the first surface enhances the adhesion of the metal-comprising layer to the barrier layer. The method is particularly useful in obtaining excellent adhesion of a copper nucleation layer to an underlying barrier layer surface.
    Type: Application
    Filed: December 17, 2001
    Publication date: August 29, 2002
    Inventors: Srinivas Gandikota, Dennis Cong, Liang Chen, Sesh Ramaswami, Daniel Carl
  • Patent number: 6362099
    Abstract: The present invention provides a method for improving the adhesion of copper and other metal-comprising conductive metals to a barrier layer. A barrier layer is provided that has a first surface that is substantially unoxidized, wherein at least a portion of the first surface is free from the presence of oxygen atoms. A conductive layer is then deposited onto the first surface of the barrier layer. The substantially unoxidized state of the first surface enhances the adhesion of the metal-comprising layer to the barrier layer. The method is particularly useful in obtaining excellent adhesion of a copper nucleation layer to an underlying barrier layer surface.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: March 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Dennis Cong, Liang Chen, Sesh Ramaswami, Daniel Carl