Patents by Inventor Seshadri Subbanna

Seshadri Subbanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9643181
    Abstract: A microfluidic system-on-a-chip includes signal processing, light generation and detection, and fluid handling functions formed on a single substrate. The disclosed integrated system has a smaller footprint than device structures where individual components are manufactured separately and then assembled. Moreover, the integrated system obviates alignment challenges associated with conventionally packaged architecture.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hung-Yang Chang, Ning Li, Fei Liu, Qiqing C. Ouyang, Seshadri Subbanna, Yajuan Wang
  • Publication number: 20120295417
    Abstract: A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Katherina E. Babich, Stephen W. Bedell, Joel P. de Souza, Gerald W. Gibson, Alexander Reznicek, Devendra K. Sadana, Seshadri Subbanna
  • Patent number: 7053460
    Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: May 30, 2006
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, Seshadri Subbanna, Robert A. Groves, John C. Malinowski, Kenneth J. Stein, Kevin S. Petrarca
  • Patent number: 6933186
    Abstract: A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Kenneth J. Stein, Seshadri Subbanna, Richard P. Volant
  • Patent number: 6927476
    Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 9, 2005
    Assignee: Internal Business Machines Corporation
    Inventors: Gregory G. Freeman, Seshadri Subbanna, Basanth Jagannathan, Kathryn T. Schonenberg, Shwu-Jen Jeng, Kenneth J. Stein, Jeffrey B. Johnson
  • Patent number: 6858532
    Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: February 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Wesley C. Natzle, David C. Ahlgren, Steven G. Barbee, Marc W. Cantell, Basanth Jagannathan, Louis D. Lanzerotti, Seshadri Subbanna, Ryan W. Wuthrich
  • Patent number: 6800503
    Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Joseph T. Kocis, James Tornello, Kevin S. Petrarca, Richard Volant, Seshadri Subbanna
  • Patent number: 6800921
    Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Gregory Gower Freeman, Seshadri Subbanna
  • Patent number: 6798029
    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: September 28, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, John C. Bisson, Donna R. Cote, Timothy J. Dalton, Robert A. Groves, Kevin S. Petrarca, Kenneth J. Stein, Seshadri Subbanna
  • Patent number: 6780695
    Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: August 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Seshadri Subbanna, Basanth Jagannathan, Gregory G. Freeman, David C. Ahlgren, David Angell, Kathryn T. Schonenberg, Kenneth J. Stein, Fen F. Jamin
  • Patent number: 6777302
    Abstract: A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced width is achieved without the need of using advanced lithographic tools and/or advanced photomasks.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: August 17, 2004
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, David Angell, Seshadri Subbanna
  • Publication number: 20040126921
    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.
    Type: Application
    Filed: May 9, 2003
    Publication date: July 1, 2004
    Inventors: Richard P. Volant, John C. Bisson, Donna R. Cote, Timothy J. Dalton, Robert A. Groves, Kevin S. Petrarca, Kenneth J. Stein, Seshadri Subbanna
  • Publication number: 20040110354
    Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wesley C. Natzle, David C. Ahlgren, Steven G. Barbee, Marc W. Cantell, Basanth Jagannathan, Louis D. Lanzerotti, Seshadri Subbanna, Ryan W. Wuthrich
  • Publication number: 20040097003
    Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 20, 2004
    Applicant: International Business Machines Corporation
    Inventors: Joseph T. Kocis, James Tornello, Kevin S. Petrarca, Richard Volant, Seshadri Subbanna
  • Publication number: 20040077140
    Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
  • Patent number: 6696343
    Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: February 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Robert A. Groves, Kenneth J. Stein, Seshadri Subbanna, Richard P. Volant
  • Patent number: 6670228
    Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Gregory Gower Freeman, Seshadri Subbanna
  • Patent number: 6661069
    Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Robert A. Groves, Kenneth J. Stein, Seshadri Subbanna, Richard P. Volant
  • Patent number: 6635506
    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: October 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, John C. Bisson, Donna R. Cote, Timothy J. Dalton, Robert A. Groves, Kevin S. Petrarca, Kenneth J. Stein, Seshadri Subbanna
  • Publication number: 20030148550
    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.
    Type: Application
    Filed: November 7, 2001
    Publication date: August 7, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard P. Volant, John C. Bisson, Donna R. Cote, Timothy J. Dalton, Robert A. Groves, Kevin S. Petrarca, Kenneth J. Stein, Seshadri Subbanna