Patents by Inventor Seshagiri Prasad Kalluri

Seshagiri Prasad Kalluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10571989
    Abstract: A data collection system includes one or more input sensing devices and a data collection device. The data collection device includes data collection circuitry that is continuously activated to capture measurement data samples from the one or more input sensing devices and locally store the measurement data samples. The data collection device also includes a digital processor that is coupled to the data collection circuitry and is activated to locally perform a sample analysis of the measurement data samples, wherein the sample analysis is a regular analysis of routine measurement data samples when the measurement data samples are without a triggering event, and wherein the sample analysis is an event analysis when the measurement data samples include a triggering event. A data collection integrated circuit and a measurement data sample collection method are also included.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 25, 2020
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Seshagiri Prasad Kalluri, Vijayanand Angarai, Adam Christopher Krolnik, Venkata Krishna Vemireddy
  • Publication number: 20190073014
    Abstract: A data collection system includes one or more input sensing devices and a data collection device. The data collection device includes data collection circuitry that is continuously activated to capture measurement data samples from the one or more input sensing devices and locally store the measurement data samples. The data collection device also includes a digital processor that is coupled to the data collection circuitry and is activated to locally perform a sample analysis of the measurement data samples, wherein the sample analysis is a regular analysis of routine measurement data samples when the measurement data samples are without a triggering event, and wherein the sample analysis is an event analysis when the measurement data samples include a triggering event. A data collection integrated circuit and a measurement data sample collection method are also included.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Inventors: Seshagiri Prasad Kalluri, Vijayanand Angarai, Adam Christopher Krolnik, Venkata Krishna Vemireddy
  • Patent number: 8516605
    Abstract: The present invention provides for a security system for an electronic device that, in one embodiment, includes a processor with a software access key encrypted thereon and a software application with a processor access key encoded therein so that operation of the electronic device and execution of the software application requires both the software access key and the processor access key.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 20, 2013
    Assignee: Verisilicon Holdings Co., Ltd.
    Inventors: Seshagiri Prasad Kalluri, Danny W. Wilson, Adam Christopher Krolnik
  • Patent number: 7607057
    Abstract: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: October 20, 2009
    Assignee: LSI Corporation
    Inventors: Mark Allen Boike, Seshagiri Prasad Kalluri, Vijayanand J. Angarai, David Mark Brantley, Scott Avery Beeker
  • Patent number: 7434036
    Abstract: A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional execution instruction specifies one or more instructions to be conditionally executed (i.e., “target instructions”), a register of the processor, and a condition within the register. When the instruction unit fetches and decodes the conditional execution instruction, the execution unit saves results of the one or more target instructions dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction. A system including the processor is described, as is a method for conditionally executing at least one instruction.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: October 7, 2008
    Assignee: VeriSilicon Holdings Co. Ltd.
    Inventors: Shannon A. Wichman, Seshagiri Prasad Kalluri
  • Publication number: 20080219440
    Abstract: The present invention provides for a security system for an electronic device that, in one embodiment, includes a processor with a software access key encrypted thereon and a software application with a processor access key encoded therein so that operation of the electronic device and execution of the software application requires both the software access key and the processor access key.
    Type: Application
    Filed: August 8, 2007
    Publication date: September 11, 2008
    Applicant: VeriSilicon Holdings Company Ltd.
    Inventors: Seshagiri Prasad Kalluri, Danny W. Wilson, Adam Christopher Krolnik
  • Patent number: 6081915
    Abstract: Method and apparatus for reducing the time required to test an integrated circuit (10) using slew rate control. Using a very slow slew rate during normal operation may reduce electromagnetic interference, while using a faster slew rate during testing may reduce the test costs. In one embodiment, terminal control circuitry (40) includes a fast test control bit (50) to select a slow slew rate during normal operation, to select a faster slew rate during functional testing, and to optionally select a variety of slew rates during a special test to more fully characterize the behavior of integrated circuit (10). In one embodiment, each pre-driver circuit (80, 81) includes a low resistance device (61, 63) which may be selectively enabled or disabled to join with capacitors (66, 67) in output driver (82) to affect the slew rate of the signal driven as an output by integrated circuit terminal (83).
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: June 27, 2000
    Assignee: Motorola, Inc.
    Inventors: Seshagiri Prasad Kalluri, Rene Martin Delgado
  • Patent number: 6052746
    Abstract: Method and apparatus for selectively enabling a pull device coupled to a multiplexed terminal connector based on the function of the terminal connector. When the terminal functions as a general purpose input/output (GPIO), the pull device is enabled on reset or on setting a control bit. For operation as a data port, the pull device is disabled, and on reset the pull device is enabled only after any pending data transaction has completed. Upon completion of the reset period the pull device is again disabled for data port operation. In one embodiment, a terminal has a first interruptible function and a second uninterruptible function. The terminal is coupled to a pull device and control logic. If the second function is active, the control logic enables the pull device with a time delay sufficient that the second function is completed prior to the enabling of the pull device.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: April 18, 2000
    Assignee: Motorola, Inc.
    Inventors: Seshagiri Prasad Kalluri, Rene M. Delgado, James B. Eifert