Abstract: Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Abstract: Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

Abstract: Various implementations described herein are related to a device having an output pad that is configured to supply an output pad voltage. The device may include tracking circuitry that is configured to receive a first voltage, receive a second voltage that is different than the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the feedback voltage. The device may include output circuitry that is configured to receive the first tracking voltage and the second tracking voltage from the tracking circuitry and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

Abstract: Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Abstract: Various implementations described herein are related to a device having a level shifting circuit that shifts an input voltage in a first domain to an output voltage in a second domain, and also, the level shifting circuit may shift the input voltage to the output voltage based on a first level shifting response. The device may also include a boost circuit that increases the input voltage and provides a boosted input voltage to the level shifting circuit so that the level shifting circuit shifts the input voltage to the output voltage based on the boosted input voltage.

Abstract: Various implementations described herein are related to a device having a level shifting circuit that shifts an input voltage in a first domain to an output voltage in a second domain, and also, the level shifting circuit may shift the input voltage to the output voltage based on a first level shifting response. The device may also include a boost circuit that increases the input voltage and provides a boosted input voltage to the level shifting circuit so that the level shifting circuit shifts the input voltage to the output voltage based on the boosted input voltage.

Abstract: Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

Abstract: Various implementations described herein are related to a device having an output pad that is configured to supply an output pad voltage. The device may include tracking circuitry that is configured to receive a first voltage, receive a second voltage that is different than the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the feedback voltage. The device may include output circuitry that is configured to receive the first tracking voltage and the second tracking voltage from the tracking circuitry and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Abstract: Briefly, embodiments of claimed subject matter relate to controlling a voltage across a circuit element utilized in a pre-driver for a bidirectional communications bus. In embodiments, a voltage control circuit may be utilized to reduce electrical stress across a capacitor coupled to the pre-driver to the communications bus. The voltage control circuit may operate to provide a voltage to a middle point between two capacitors, of a plurality of capacitors, which may operate to limit voltage across one or more capacitors to below a predetermined limit.

Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.