Patents by Inventor Seshu B. Desu
Seshu B. Desu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6495208Abstract: Nanocomposite thin films with low dielectric constants are made by the simultaneous deposition of an oxide dielectric and an organic polymer at near room temperatures. Suitable oxides include SiO2, and suitable organic polymers include poly(chloro-para-xylylene). The two dielectric materials, when deposited, form nanocomposites characterized by nanometer-sized domains of dielectric material. The nanocomposite thin films of this invention are useful as dielectric layers for interlevel dielectric (ILD) and intermetal dielectric (IMD) dielectrics in the manufacture of semiconductor devices as well as for thin films for flat panel displays, food wraps, hybrid ceramics, glass, hard disk drives, and optical disk drives. Additionally, the invention comprises semiconductor devices and semiconductor chips made incorporating nanocomposites deposited by chemical vapor deposition.Type: GrantFiled: September 9, 1999Date of Patent: December 17, 2002Assignee: Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, John J. Senkevich
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Publication number: 20020081441Abstract: This invention discloses methods for the deposition of SiO2 and other oxide dielectric materials using a near room temperature thermal chemical vapor deposition process. The films have chemical, physical, optical, and electrical properties similar to or better than those of oxide films deposited using conventional, high temperature thermal CVD methods. The films of the invention are useful in the manufacture of semiconductor devices of sub-micron feature size and for food packaging.Type: ApplicationFiled: September 14, 2001Publication date: June 27, 2002Applicant: Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, John J. Senkevich
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Publication number: 20020076562Abstract: Multilayer thin films consisting of alternating layers of oxide and organic polymer dielectric materials are manufactured by chemical vapor deposition using a CVD apparatus comprising separate precursor volatilization/dissociation areas. Methods are described for the manufacture of multilayered films. The electrical properties of the multilayered films make the films of embodiments of this invention suitable for use as dielectric materials for semiconductor manufacture. The multilayered films of embodiments this invention reduce RC delay and cross-talk, thereby permitting increased density, higher frequency performance and greater reliability of semiconductor devices for use in the electronics industry.Type: ApplicationFiled: September 17, 2001Publication date: June 20, 2002Applicant: Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, John J. Senkevich
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Patent number: 6358863Abstract: Multilayer thin films consisting of alternating layers of oxide and organic polymer dielectric materials are manufactured by chemical vapor deposition using a CVD apparatus comprising separate precursor volatilization/dissociation areas. Methods are described for the manufacture of multilayered films. The electrical properties of the multilayered films make the films of embodiments of this invention suitable for use as dielectric materials for semiconductor manufacture. The multilayered films of embodiments this invention reduce RC delay and cross-talk, thereby permitting increased density, higher frequency performance and greater reliability of semiconductor devices for use in the electronics industry.Type: GrantFiled: April 30, 1999Date of Patent: March 19, 2002Assignee: Quester Technology, Inc.Inventors: Seshu B. Desu, John J. Senkevich
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Patent number: 6316055Abstract: This invention discloses methods for the deposition of SiO2 and other oxide dielectric materials using a near room temperature thermal chemical vapor deposition process. The films have chemical, physical, optical, and electrical properties similar to or better than those of oxide films deposited using conventional, high temperature thermal CVD methods. The films of the invention are useful in the manufacture of semiconductor devices of sub-micron feature size and for food packaging.Type: GrantFiled: April 30, 1999Date of Patent: November 13, 2001Assignee: Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, John J. Senkevich
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Patent number: 6139780Abstract: A charge storage device is resistant to degradation in reducing atmospheres for use in dynamic random access memories. The device consists of a dielectric layer that is sandwiched between two electrodes and grown on a suitable substrate such as silicon or silicon coated with silicon dioxide. The dielectric layer is either (a) a modified composition of Ba.sub.x Sr.sub.1-x TiO.sub.3, 0<x<1 (BST) doped with acceptor type dopants such as Mn, Co, Mg, Cr, Ga and Fe ions as the dielectric layer in the capacitor; the acceptor ions can occupy the titanium sites to prevent the formation of Ti.sup.3+ and inhibit the formation of conductive BST by compensating the charges of the oxygen vacancies, and by trapping the free electrons more freely than Ti.sup.4+, or (b) modified dielectric compositions with alkaline-earth ions with compositions [(Ba.sub.x M.sub.x)O].sub.y TiO.sub.2 (where M can be Ca, Sr or Mg) with the value of y slightly larger than unity.Type: GrantFiled: May 28, 1998Date of Patent: October 31, 2000Assignee: Sharp Kabushiki KaishaInventors: Seshu B. Desu, Carlos A. Suchicital, Dilip P. Vijay
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Patent number: 6071555Abstract: Thin films of ferroelectric composite material comprising barium strontium titanate (BSTO) combined with magnesium oxide additive are produced by metalorganic decomposition. The barium strontium titanate magnesium oxide ferroelectric composite comprises Ba.sub.1-x Sr.sub.x TiO.sub.3 /MgO, wherein x is greater than 0.0 but less than or equal to 0.75 and preferably is 0.4, and wherein the weight ratio of BSTO to magnesium oxide may range from 99 to 40 weight percent BSTO to 1 to 60 weight percent magnesium oxide. These films have desirable electronic properties and may have application to both active microwave and dynamic random access memory devices, including low dielectric constant, low loss factor, high tunability, and high resistivity. The films produced are uniformly thick and impurity free, with thicknesses of only 0.4 microns.Type: GrantFiled: November 5, 1998Date of Patent: June 6, 2000Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Somnath Sengupta, Steven Stowell, Louise Sengupta, Pooran C. Joshi, Sasangan Ramanathan, Seshu B. Desu
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Patent number: 6048737Abstract: A ferroelectric capacitor taking a multilayer structure wherein a conductive oxide layer which is formed between a metal electrode and a ferroelectric layer, capable of enhancing the fatigue behavior in addition to reducing the leakage current. The multilayer structure can be fabricated by depositing a silicon oxide (SiO.sub.2) layer, an adhesive layer, a bottom metal layer, a lower conductive oxide layer, a ferroelectric layer, an upper conductive oxide layer and a top metal electrode layer are deposited over a silicon substrate, in sequence.Type: GrantFiled: September 3, 1996Date of Patent: April 11, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Il-sub Chung, In-kyung Yoo, Chi-won Chung, Seshu B. Desu
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Patent number: 5873977Abstract: A method of patterning layered structure oxide thin films involving placing the layered structure thin film (with or without a mask) laid on a substrate into a chamber which is partially filled with CHC1FCF.sub.3 gas and producing a glow discharge to cause the etching of the thin film ferroelectric material. The method provides high etch rates, good etch anisotropy and good etch uniformity. For example, for SBT and SBN thin films, the etch process provides etch rates in the range of 2.5 to 17.5 nm/min depending on the etch conditions and minimal etch residues at the end of the etch process is removed easily by low temperature (250.degree. C.) baking. Also, the method provides good etch selectivity in the films and minimal surface damage.Type: GrantFiled: February 22, 1995Date of Patent: February 23, 1999Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, Wei Pan
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Patent number: 5817170Abstract: A process for producing a ferroelectric lead zirconate titanate dielectric for a semiconductor device by applying a lead titanate seeding layer to a substrate before applying the lead zirconate titanate film, and a semiconductor device produced in accordance with the process. The lead titanate seeding layer allows the subsequent lead zirconate titanate to be annealed at a significantly lower seeding temperature, to lessen interdiffusion among the films, electrodes and substrate and to lessen thermal stresses.Type: GrantFiled: August 29, 1994Date of Patent: October 6, 1998Assignees: Ceram Incorporated, Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, Chi Kong Kwok
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Patent number: 5807774Abstract: A ferroelectric capacitor device and method of manufacture. A substrate supports a bottom electrode structure, with an adhesion/diffusion barrier layer sandwiched therebetween. The electrode layer includes a metal or metal alloy and an oxide of the metal or alloy. The adhesion/diffusion barrier layer is a similar oxide. Ferroelectric material is sandwiched between a top electrode. The top layer includes a metal or metal alloy and an oxide of the same; the metal or metal alloy may be the same as the bottom electrode but need not be. The metal and metal oxide electrodes may be deposited by known deposition techniques, or the metal may be deposited and the oxide formed by annealing in oxygen ambient environment.Type: GrantFiled: December 6, 1996Date of Patent: September 15, 1998Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, Hemanshu D. Bhatt, Dilip P. Vijay
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Patent number: 5790366Abstract: A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode.Type: GrantFiled: December 6, 1996Date of Patent: August 4, 1998Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual PropertiesInventors: Seshu B. Desu, Hemanshu D. Bhatt, Dilip P. Vijay, Yoosang Hwang
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Patent number: 5717234Abstract: A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru (C.sub.5 H.sub.5).sub.2.Type: GrantFiled: January 16, 1997Date of Patent: February 10, 1998Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Jie Si, Seshu B. Desu, Chien-Hsiung Peng
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Patent number: 5688980Abstract: An organometallic lead precursor, represented by following formula:L.sub.x .multidot.Pb(THD).sub.2 ?I!wherein L is an electron donor ligand selected from the group consisting of NR.sub.3 (R=H, CH.sub.3) gas and Cl.sub.2 gas; THD denotes 2,2',6,6'-tetramethyl-3,5-heptanedione; and x is in the range of 0.5 to 2, is prepared by flowing a gas phase electron donor into a bubbler containing bis (2,2',6,6'-tetramethyl-3,5-heptanedione)Pb at a predetermined temperature, to synthesize, in-situ, an adduct. The precursor exhibits a remarkable improvement in volatility and in stability at the vaporization point.Lead-titanium based thin films prepared from the precursor, display superior reproducibility and reliability.Type: GrantFiled: October 10, 1996Date of Patent: November 18, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-in Lee, Jun-ki Lee, Seshu B. Desu
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Patent number: 5637352Abstract: An organometallic lead precursor, represented by following formula:L.sub.x.Pb(THD).sub.2 [I]wherein L is an electron donor ligand selected from the group consisting of NR.sub.3 (R=H, CH.sub.3) gas and Cl.sub.2 gas; THD denotes 2,2',6,6'-tetramethyl-3,5-heptanedione; and x is in the range of 0.5 to 2, is prepared by flowing a gas phase electron donor into a bubbler containing bis (2,2',6,6'-tetramethyl-3,5-heptanedione)Pb at a predetermined temperature, to synthesize, in-situ, an adduct. The precursor exhibits a remarkable improvement in volatility, and in stability at the vaporization point.Lead-titanium based thin films prepared from the precursor, display superior reproducibility and reliability.Type: GrantFiled: October 5, 1995Date of Patent: June 10, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-in Lee, Jun-ki Lee, Seshu B. Desu
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Patent number: 5629229Abstract: A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2.Type: GrantFiled: July 12, 1995Date of Patent: May 13, 1997Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Jie Si, Seshu B. Desu, Chien-Hsiung Peng
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Patent number: 5625587Abstract: A ferroelectric memory device having a perovskite thin film of a rare earth manganate and processes for manufacturing the same. The perovskite thin film layer has properties consistent with high quality nonvolatile memory devices. The perovskite thin film layer can be applied by a MOCVD process, by a MOD process, or a liquid source delivery process, all of which are described.Type: GrantFiled: July 12, 1995Date of Patent: April 29, 1997Assignee: Virginia Polytechnic Institute and State UniversityInventors: Chien-Hsiung Peng, Seshu B. Desu, Jie Si
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Patent number: 5593727Abstract: The chemical vapor deposition of hydridospherosiloxane to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. The chemical vapor deposition process synthesized compounds with the general formula,(HSiO.sub.3/2).sub.n,with n being an even number ranging from 8 to a very large number. More particularly, it relates to the vapor deposition of oligomeric hydrogensilsesquioxanes, henceforth referred to as hydridospherosiloxanes. The hydridospherosiloxanes are used directly in a chemical vapor deposition reactor to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. Hydridospherosiloxanes and soluble hydrogensilsesquioxane resin are produced having the formula(HSiO.sub.3/2).sub.n,where n is an even integer greater than 8.Type: GrantFiled: November 8, 1993Date of Patent: January 14, 1997Assignee: Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, Chien-Hsiung Peng, Tian Shi, Pradyot A. Agaskar
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Patent number: 5527567Abstract: A method of fabricating high quality layered structure oxide ferroelectric thin films. The deposition process is a chemical vapor deposition process involving chemical reaction between volatile metal organic compounds of various elements comprising the layered structure material to be deposited, with other gases in a reactor, to produce a nonvolatile solid that deposits on a suitably placed substrate such as a conducting, semiconducting, insulating, or complex integrated circuit substrate. The source materials for this process may include organometallic compounds such as alkyls, alkoxides, .beta.-diketonates or metallocenes of each individual element comprising the layered structure material to be deposited and oxygen. Preferably, the reactor in which the deposition is done is either a hot wall or a cold wall reactor and the vapors are introduced into this reactor either through a set of bubblers or through a direct liquid injection system.Type: GrantFiled: May 30, 1995Date of Patent: June 18, 1996Assignees: Ceram Incorporated, Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, IncInventors: Seshu B. Desu, Wei Tao, Chien H. Peng, Tingkai Li, Yongfei Zhu
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Patent number: 5496437Abstract: A method of reactive ion etching both a lead zirconate titanate ferroelectric dielectric and a RuO.sub.2 electrode, and a semiconductor device produced in accordance with such process. The dielectric and electrode are etched in an etching gas of O.sub.2 mixed with either CClF.sub.2 or CHClFCF.sub.3.Type: GrantFiled: June 10, 1993Date of Patent: March 5, 1996Assignees: Ceram Incorporated, Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.Inventors: Seshu B. Desu, Wei Pan, Dilip P. Vijay