Abstract: Devices and methods are disclosed for detecting which of a multiple ports of a storage device is connected to a host system using a shared detection line. In certain embodiments, a storage device includes non-volatile memory, a first data port, a second data port having a faster data transfer speed, a shared detection line, and control circuitry. The control circuitry can be configured to detect voltage on the shared detection line in response to a connection of at least one of the first data port and the second data port to the host system, determine which of the first data port or the second data port is connected to the host system, and establish a data connection with the host system at the first data transfer speed or the second data transfer speed based on the port connected to the host system.

Abstract: Devices and methods are disclosed for detecting which of a multiple ports of a storage device is connected to a host system using a shared detection line. In certain embodiments, a storage device includes non-volatile memory, a first data port, a second data port having a faster data transfer speed, a shared detection line, and control circuitry. The control circuitry can be configured to detect voltage on the shared detection line in response to a connection of at least one of the first data port and the second data port to the host system, determine which of the first data port or the second data port is connected to the host system, and establish a data connection with the host system at the first data transfer speed or the second data transfer speed based on the port connected to the host system.

Abstract: A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.

Abstract: A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.

Abstract: An integrated circuit includes a bus (905), processor coupled to the bus (910), a peripheral coupled to the bus (930), and a performance tracking module (215) configured to detect bus events and non-bus related events. The performance tracking module is configured to determine a bus performance metric from the bus events and a non-bus performance metric from the non-bus related events.