Patents by Inventor Seth E. Lederer

Seth E. Lederer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12625705
    Abstract: A present invention embodiment provides a cache line hold state that reduces cache contention. A first processor executes a store instruction to acquire a lock on a cache line in a shared memory system of a multiprocessor computing system. The first processor sets the cache line to an exclusive state in a local cache of the first processor upon successful acquisition of the lock. A lock state indicative of a windowed hold on the cache line is recorded by the first processor, wherein the windowed hold enables non-exclusive fetch requests from one or more other processors.
    Type: Grant
    Filed: December 13, 2024
    Date of Patent: May 12, 2026
    Assignee: International Business Machines Corporation
    Inventors: Michael Fee, Deanna Postles Dunn Berger, Peter Kenneth Szwed, Seth E. Lederer, Aaron Tsai, Timothy J Slegel, Jason D Kohl, Robert J Sonnelitter, III, Gregory William Alexander, Andrew Walter Piechowski
  • Patent number: 12561421
    Abstract: An instruction to be executed within the computing environment is obtained. The instruction includes an operation code indicating a diagnose operation. The instruction is executed. The executing includes obtaining a token as an input to the instruction and comparing the token to a current token for a configuration of the computing environment. Based on the token matching the current token, one or more verification certificates are returned from a certificate store.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: February 24, 2026
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis P. Gomes, David Harold Surman, Peter Jeremy Relson, Seth E. Lederer, Thomas Mathias
  • Publication number: 20260050451
    Abstract: Execution of an instruction includes obtaining software objects and loading instructions into a memory and storing the workload type attribute for each software object. The execution includes operations that during runtime, deploy a first hardware instruction to trigger a firmware process to sample, at each interval of timed pre-configured intervals, instructions from the sets of instructions of the one or more software objects being executed during the interval by one or more processors of the computing system. The operations include deploying a second hardware instruction to obtain and store samples from the firmware process in the memory. The operations include generating, based on analyzing the stored samples, execution parameters associated with each sample. The operations include determining accesses to the software libraries in the computing system, by workload type attribute. The operations automatically implement an action related to at least one software object in the computing system.
    Type: Application
    Filed: August 13, 2024
    Publication date: February 19, 2026
    Inventors: Nicholas R. JONES, Brenton BELMAR, Jonathan D. BRADBURY, Michael Joseph CADIGAN, JR., Eberhard ENGLER, Joseph GENTILE, Bruce Conrad GIAMEI, Lisa Cranton HELLER, Christian JACOBI, Edward A. KING, Seth E. LEDERER, Cedric LICHTENAU, Gary S. PUCHKOFF, Andrew M. SICA, Timothy J. SLEGEL, Robert W. ST. JOHN, Kevin A. STOODLEY, Elpida TZORTZATOS
  • Publication number: 20250342067
    Abstract: A method includes receiving a request to create a logical partition. The method further includes determining whether the logical partition can be implemented on a single drawer of a plurality of drawers. The method further includes, responsive to determining that the logical partition can be implemented on a single drawer of the plurality of drawers, allocating the logical partition to one of the drawers of the plurality of drawers based on a container size that can fit the logical partition. The method further includes, responsive to determining that the logical partition cannot be implemented on a single drawer of the plurality of drawers, allocating the logical partition to at least two drawers of the plurality of drawers using bitmasks, wherein each of the bitmasks represents a processor chip of a plurality of processor chips, and wherein one bitmask is generated per drawer of the plurality of drawers.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 6, 2025
    Inventors: Jeffrey G. Chan, Seth E. Lederer, Jerry A. Moody, Brian Fernandez, David Shane Hutton
  • Patent number: 12147304
    Abstract: An instruction that includes an operation code indicating a diagnose operation is obtained and executed within a computing environment. The executing the instruction includes retrieving selected data from a dump save area to be used to restore machine state and restoring the machine state. The restoring includes storing the selected data in a selected location. One or more storage keys used to protect access to the selected data are restored.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis P. Gomes, David Harold Surman, Seth E. Lederer, James H. Mulder
  • Patent number: 12118387
    Abstract: A query operation is performed to obtain information for a select entity of a computing environment. The information includes boost information of one or more boost features currently available for the select entity. The one or more boost features are to be used to temporarily adjust one or more processing attributes of the select entity. The boost information obtained from performing the query operation is provided in an accessible location to be used to perform one or more actions to facilitate processing in the computing environment.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 15, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Omkar Ulhas Javeri, David Harold Surman, Seth E. Lederer, Peter Jeremy Relson, Jonathan D. Bradbury, Hunter J. Kauffman, Martin Stock, Brent J Boisvert
  • Publication number: 20240289428
    Abstract: An instruction to be executed within the computing environment is obtained. The instruction includes an operation code indicating a diagnose operation. The instruction is executed. The executing includes obtaining a token as an input to the instruction and comparing the token to a current token for a configuration of the computing environment. Based on the token matching the current token, one or more verification certificates are returned from a certificate store.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 29, 2024
    Inventors: Louis P. GOMES, David Harold SURMAN, Peter Jeremy RELSON, Seth E. LEDERER, Thomas MATHIAS
  • Publication number: 20240281335
    Abstract: An instruction that includes an operation code indicating a diagnose operation is obtained and executed within a computing environment. The executing the instruction includes retrieving selected data from a dump save area to be used to restore machine state and restoring the machine state. The restoring includes storing the selected data in a selected location. One or more storage keys used to protect access to the selected data are restored.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Louis P. GOMES, David Harold SURMAN, Seth E. LEDERER, James H. MULDER
  • Patent number: 11983576
    Abstract: A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: May 14, 2024
    Inventors: Omkar Ulhas Javeri, Peter Dana Driever, Brian Keith Wade, Seth E. Lederer
  • Patent number: 11782872
    Abstract: Logical processor distribution across physical processors is provided. A set of logical processors of a number of logical processors defined for a particular logical partition of a plurality of active logical partitions is assigned to a physical processor chip having a greatest logical processor entitlement for the particular logical partition until no more logical processors can be assigned to that physical processor chip based on a logical processor entitlement of that physical processor chip being exhausted. Remaining logical processors of the number of logical processors defined for the particular logical partition are assigned to other physical processor chips of a plurality of physical processor chips assigned to the particular logical partition until all of the remaining logical processors have been assigned to a physical processor chip.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey G. Chan, Seth E. Lederer, Jerry A. Moody, Hunter J. Kauffman
  • Publication number: 20230281158
    Abstract: Logical processor distribution across physical processors is provided. A set of logical processors of a number of logical processors defined for a particular logical partition of a plurality of active logical partitions is assigned to a physical processor chip having a greatest logical processor entitlement for the particular logical partition until no more logical processors can be assigned to that physical processor chip based on a logical processor entitlement of that physical processor chip being exhausted. Remaining logical processors of the number of logical processors defined for the particular logical partition are assigned to other physical processor chips of a plurality of physical processor chips assigned to the particular logical partition until all of the remaining logical processors have been assigned to a physical processor chip.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Inventors: Jeffrey G. Chan, Seth E. Lederer, Jerry A. Moody, Hunter J. Kauffman
  • Publication number: 20230176925
    Abstract: A computer implemented method for managing virtual processor pools includes identifying a set of available system resources, defining a set of virtual resource pools, assigning one or more system resources of the set of identified system resources to one or more virtual pools of the set of virtual resource pools, creating a plurality of logical partitions within a first virtual resource pool of the set of virtual resource pools, wherein each logical partition of the plurality of logical partitions specifies a weight relative to other partitions in the first virtual resource pool, receiving a request for additional resources from the first virtual resource pool, and allowing the first virtual resource pool to access an unused resource from a second virtual resource pool of the set of virtual resource pools. A computer program product and computer system corresponding to the method are also disclosed herein.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Seth E. Lederer, Jeffrey G. Chan, Hunter J. Kauffman, Jeffrey Paul Kubala, Daniel Henry Lepore
  • Publication number: 20230040725
    Abstract: A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Omkar Ulhas Javeri, Peter Dana Driever, Brian Keith Wade, Seth E. Lederer
  • Publication number: 20230043202
    Abstract: A query operation is performed to obtain information for a select entity of a computing environment. The information includes boost information of one or more boost features currently available for the select entity. The one or more boost features are to be used to temporarily adjust one or more processing attributes of the select entity. The boost information obtained from performing the query operation is provided in an accessible location to be used to perform one or more actions to facilitate processing in the computing environment.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Omkar Ulhas Javeri, David Harold Surman, Seth E. Lederer, Peter Jeremy Relson, Jonathan D. Bradbury, Hunter J. Kauffman, Martin Stock, Brent J. Boisvert
  • Patent number: 11256531
    Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Muruganandam Somasundaram, Jeffrey Paul Kubala, Seth E. Lederer, Jeffrey G. Chan, Jerry A. Moody
  • Publication number: 20200401435
    Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Muruganandam Somasundaram, Jeffrey Paul Kubala, Seth E. Lederer, Jeffrey G. Chan, Jerry A. Moody