Patents by Inventor Seth E. Lederer

Seth E. Lederer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12147304
    Abstract: An instruction that includes an operation code indicating a diagnose operation is obtained and executed within a computing environment. The executing the instruction includes retrieving selected data from a dump save area to be used to restore machine state and restoring the machine state. The restoring includes storing the selected data in a selected location. One or more storage keys used to protect access to the selected data are restored.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis P. Gomes, David Harold Surman, Seth E. Lederer, James H. Mulder
  • Patent number: 12118387
    Abstract: A query operation is performed to obtain information for a select entity of a computing environment. The information includes boost information of one or more boost features currently available for the select entity. The one or more boost features are to be used to temporarily adjust one or more processing attributes of the select entity. The boost information obtained from performing the query operation is provided in an accessible location to be used to perform one or more actions to facilitate processing in the computing environment.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 15, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Omkar Ulhas Javeri, David Harold Surman, Seth E. Lederer, Peter Jeremy Relson, Jonathan D. Bradbury, Hunter J. Kauffman, Martin Stock, Brent J Boisvert
  • Patent number: 11983576
    Abstract: A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: May 14, 2024
    Inventors: Omkar Ulhas Javeri, Peter Dana Driever, Brian Keith Wade, Seth E. Lederer
  • Patent number: 11782872
    Abstract: Logical processor distribution across physical processors is provided. A set of logical processors of a number of logical processors defined for a particular logical partition of a plurality of active logical partitions is assigned to a physical processor chip having a greatest logical processor entitlement for the particular logical partition until no more logical processors can be assigned to that physical processor chip based on a logical processor entitlement of that physical processor chip being exhausted. Remaining logical processors of the number of logical processors defined for the particular logical partition are assigned to other physical processor chips of a plurality of physical processor chips assigned to the particular logical partition until all of the remaining logical processors have been assigned to a physical processor chip.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey G. Chan, Seth E. Lederer, Jerry A. Moody, Hunter J. Kauffman
  • Publication number: 20230281158
    Abstract: Logical processor distribution across physical processors is provided. A set of logical processors of a number of logical processors defined for a particular logical partition of a plurality of active logical partitions is assigned to a physical processor chip having a greatest logical processor entitlement for the particular logical partition until no more logical processors can be assigned to that physical processor chip based on a logical processor entitlement of that physical processor chip being exhausted. Remaining logical processors of the number of logical processors defined for the particular logical partition are assigned to other physical processor chips of a plurality of physical processor chips assigned to the particular logical partition until all of the remaining logical processors have been assigned to a physical processor chip.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Inventors: Jeffrey G. Chan, Seth E. Lederer, Jerry A. Moody, Hunter J. Kauffman
  • Publication number: 20230176925
    Abstract: A computer implemented method for managing virtual processor pools includes identifying a set of available system resources, defining a set of virtual resource pools, assigning one or more system resources of the set of identified system resources to one or more virtual pools of the set of virtual resource pools, creating a plurality of logical partitions within a first virtual resource pool of the set of virtual resource pools, wherein each logical partition of the plurality of logical partitions specifies a weight relative to other partitions in the first virtual resource pool, receiving a request for additional resources from the first virtual resource pool, and allowing the first virtual resource pool to access an unused resource from a second virtual resource pool of the set of virtual resource pools. A computer program product and computer system corresponding to the method are also disclosed herein.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Seth E. Lederer, Jeffrey G. Chan, Hunter J. Kauffman, Jeffrey Paul Kubala, Daniel Henry Lepore
  • Publication number: 20230040725
    Abstract: A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Omkar Ulhas Javeri, Peter Dana Driever, Brian Keith Wade, Seth E. Lederer
  • Publication number: 20230043202
    Abstract: A query operation is performed to obtain information for a select entity of a computing environment. The information includes boost information of one or more boost features currently available for the select entity. The one or more boost features are to be used to temporarily adjust one or more processing attributes of the select entity. The boost information obtained from performing the query operation is provided in an accessible location to be used to perform one or more actions to facilitate processing in the computing environment.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Omkar Ulhas Javeri, David Harold Surman, Seth E. Lederer, Peter Jeremy Relson, Jonathan D. Bradbury, Hunter J. Kauffman, Martin Stock, Brent J. Boisvert
  • Patent number: 11256531
    Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Muruganandam Somasundaram, Jeffrey Paul Kubala, Seth E. Lederer, Jeffrey G. Chan, Jerry A. Moody
  • Publication number: 20200401435
    Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Muruganandam Somasundaram, Jeffrey Paul Kubala, Seth E. Lederer, Jeffrey G. Chan, Jerry A. Moody