Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.

Abstract: Apparatuses, systems, and methods for tracking latch upset events using block status data are described. An example method includes tracking a block status of each of a plurality of blocks of a first memory device by storing a first set of block status data that indicates a status of each block of the plurality of blocks in the first memory device and storing a second set of block status data that indicates a status of each block of the plurality of blocks in a location. The example method further includes comparing the first set of block status data to the second set of block status data.

Abstract: Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.

Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.

Abstract: Apparatuses, systems, and methods for correcting latch upset events in a trim register are described. An example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.

Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.

Abstract: An example method can include focusing a light source onto a circuit of a first memory die of a plurality of memory dies. A light of the light source can reach the circuit of the memory die and can be reflected back toward a sensor. The method can further include receiving the reflection of light from the circuit at the sensor. The method can further include determining whether the circuit is transferring a particular signal based on the reflected light.

Abstract: An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

Abstract: An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

Abstract: Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.

Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.

Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.

Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.

Abstract: Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Abstract: Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.

Abstract: Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.