Patents by Inventor Seth L. Knupp
Seth L. Knupp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11177167Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: GrantFiled: May 10, 2016Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Daniel Edelstein, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Patent number: 10643890Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: GrantFiled: May 10, 2016Date of Patent: May 5, 2020Assignee: International Business Machines CorporationInventors: Daniel Edelstein, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Publication number: 20160276216Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: ApplicationFiled: May 10, 2016Publication date: September 22, 2016Inventors: DANIEL EDELSTEIN, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Publication number: 20160276280Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: ApplicationFiled: May 10, 2016Publication date: September 22, 2016Applicant: International Business Machines CorporationInventors: DANIEL EDELSTEIN, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Publication number: 20160268160Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: ApplicationFiled: May 10, 2016Publication date: September 15, 2016Inventors: DANIEL EDELSTEIN, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Patent number: 9331073Abstract: A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.Type: GrantFiled: September 26, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, James J. Demarest, Hong He, Seth L. Knupp, Raghavasimhan Sreenivasan, Sean Teehan, Allan W. Upham, Chih-Chao Yang
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Publication number: 20160093697Abstract: A finFET with a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The structure may include a fin having a {100} crystallographic orientation; a conformal well covering the fin; and a conformal barrier covering the conformal well.Type: ApplicationFiled: October 5, 2015Publication date: March 31, 2016Inventors: Marc A. Bergendahl, James J. Demarest, Hong He, Seth L. Knupp, Raghavasimhan Sreenivasan, Sean Teehan, Allan W. Upham, Chih-Chao Yang
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Publication number: 20160093613Abstract: A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Marc A. Bergendahl, James J. Demarest, Hong He, Seth L. Knupp, Raghavasimhan Sreenivasan, Sean Teehan, Allan W. Upham, Chih-Chao Yang
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Publication number: 20150357236Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: ApplicationFiled: June 8, 2014Publication date: December 10, 2015Inventors: Daniel Edelstein, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Patent number: 8981466Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: GrantFiled: March 11, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 8980715Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: GrantFiled: August 28, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
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Publication number: 20140256153Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: ApplicationFiled: August 28, 2013Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
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Publication number: 20140252502Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha