Abstract: The effectiveness of various types of optical proximity correction schemes for avoiding line shortening are easily evaluated by imprinting a test pattern on a semiconductor wafer. The pattern includes an easily measurable standard measurement element not susceptible to line shortening and a test element having a series of parallel lines with narrow widths comparable to the widths of the circuit features that are susceptible to line shortening. The test element also includes the same optical proximity correction scheme whose effectiveness is to be measured. The entire test pattern is photolithographed onto the wafer and the lengths of measurement element and the test element are measured and compared to determine the effectiveness of the correction. Several test patterns, each with a different form of optical proximity correction, can be lithographed onto a single wafer for a comparative review of the different correction schemes both in focus and out of focus both positively and negatively.

Abstract: Line shortening and other defects in integrated circuits are measured by imprinting accuracy determinative patterns in the scribe lines or die margins of the mask field. The patterns are ideally formed in the general nature of the usual box in a box configuration with one of the boxes being specially configured to include a series of lines and spaces having narrow widths comparable to the width of the lines to be formed in the integrated circuit. The use of the narrow lines provides the box in a box configuration with the same line shortening that the circuit feature will itself experience. Small spaces between the lines permit the standard measuring equipment to locate at the ends of the lines.