Patents by Inventor Setsuji NISHIMIYA
Setsuji NISHIMIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220208793Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.Type: ApplicationFiled: December 22, 2021Publication date: June 30, 2022Inventors: Hitoshi TAKAHATA, Tetsuo KIKUCHI, Kengo HARA, Setsuji NISHIMIYA, Masahiko SUZUKI, Tohru DAITOH
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Publication number: 20220189999Abstract: An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction.Type: ApplicationFiled: December 9, 2021Publication date: June 16, 2022Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
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Publication number: 20220181356Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.Type: ApplicationFiled: November 29, 2021Publication date: June 9, 2022Inventors: MASAHIKO SUZUKI, TETSUO KIKUCHI, SETSUJI NISHIMIYA, KENGO HARA, HITOSHI TAKAHATA, TOHRU DAITOH
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Publication number: 20220157855Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Inventors: Hajime IMAI, Tohru DAITOH, Tetsuo KIKUCHI, Masamitsu YAMANAKA, Yoshihito HARA, Tatsuya KAWASAKI, Masahiko SUZUKI, Setsuji NISHIMIYA
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Patent number: 11322105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: August 13, 2021Date of Patent: May 3, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11302718Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interpType: GrantFiled: May 11, 2018Date of Patent: April 12, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Hideki Kitagawa, Teruyuki Ueda, Masahiko Suzuki, Setsuji Nishimiya, Toshikatsu Itoh
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Patent number: 11296126Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.Type: GrantFiled: March 26, 2020Date of Patent: April 5, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Tetsuo Kikuchi, Masamitsu Yamanaka, Yoshihito Hara, Tatsuya Kawasaki, Masahiko Suzuki, Setsuji Nishimiya
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Publication number: 20220077318Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Tohru DAITOH, Hajime IMAI, Kengo HARA
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Publication number: 20220005839Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.Type: ApplicationFiled: July 1, 2021Publication date: January 6, 2022Inventors: Tohru DAITOH, Masahiko SUZUKI, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tetsuo KIKUCHI
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Patent number: 11205729Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.Type: GrantFiled: March 6, 2019Date of Patent: December 21, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Tohru Daitoh, Hajime Imai, Kengo Hara
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Publication number: 20210390920Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: August 13, 2021Publication date: December 16, 2021Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11189645Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: GrantFiled: March 26, 2018Date of Patent: November 30, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20210327911Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.Type: ApplicationFiled: April 7, 2021Publication date: October 21, 2021Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
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Publication number: 20210327923Abstract: An active matrix substrate includes a substrate, a first gate bus line, a second gate bus line, a third gate bus line, a first source bus line, a second source bus line, a first pixel region, a second pixel region, and a first source contact portion. When viewed from a normal direction of the substrate, a first opening portion is located between the second gate bus line and the third gate bus line, and a first distance D1 in a column direction between the second gate bus line and the first opening portion and a second distance D2 in the column direction between the third gate bus line and the first opening portion are both ? or more of a second interval Dy2 in the column direction between the second gate bus line and the third gate bus line.Type: ApplicationFiled: April 14, 2021Publication date: October 21, 2021Inventors: MASAHIKO SUZUKI, TETSUO KIKUCHI, SETSUJI NISHIMIYA, KENGO HARA, HITOSHI TAKAHATA, TOHRU DAITOH
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Patent number: 11145679Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.Type: GrantFiled: March 17, 2020Date of Patent: October 12, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Masamitsu Yamanaka, Teruyuki Ueda, Hitoshi Takahata
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Publication number: 20210305280Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: ApplicationFiled: March 26, 2018Publication date: September 30, 2021Inventors: Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Publication number: 20210294138Abstract: A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned.Type: ApplicationFiled: September 19, 2017Publication date: September 23, 2021Inventors: Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Toshikatsu ITOH, Teruyuki UEDA, Setsuji NISHIMIYA, Kengo HARA
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Publication number: 20210273107Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.Type: ApplicationFiled: February 24, 2021Publication date: September 2, 2021Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Masahiko SUZUKI, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA
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Patent number: 11107429Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: March 16, 2018Date of Patent: August 31, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20210249445Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.Type: ApplicationFiled: January 25, 2021Publication date: August 12, 2021Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH