Patents by Inventor Setsuko Wakimoto

Setsuko Wakimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070290267
    Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: Fuji Electric Holdings Co., Ltd
    Inventors: Koh Yoshikawa, Setsuko Wakimoto, Hitoshi Kuribayashi
  • Publication number: 20070262362
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Setsuko WAKIMOTO, Manabu TAKEI, Shinji FUJIKAKE
  • Publication number: 20070224769
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: May 29, 2007
    Publication date: September 27, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Patent number: 7262100
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: August 28, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Publication number: 20060076583
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: September 2, 2005
    Publication date: April 13, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Publication number: 20050087800
    Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.
    Type: Application
    Filed: December 14, 2004
    Publication date: April 28, 2005
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
  • Patent number: 6858500
    Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 22, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
  • Publication number: 20030164527
    Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.
    Type: Application
    Filed: December 31, 2002
    Publication date: September 4, 2003
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto