Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: An integrated circuit that performs multiple separate types of measurements is described. This integrated circuit may include a measurement circuit. Moreover, the integrated circuit may include or may be electrically coupled to at least one sensor. During operation, the integrated circuit may perform the separate types of measurements of or associated with an object in an environment with reduced or obscured information in a visual band of frequencies. For example, the environment with reduced or obscured information may include fog or a cloud. Note that performing of the separate types of measurements may include: filtering measurements based at least in part on velocity relative to ground; and providing data streams having different spatial frequencies and sampling rates based at least in part on the filtering.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.

Abstract: Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures, and a power amplifier and switch can be integrated onto a single complementary metal oxide semiconductor die.

Abstract: Embodiments of radio frequency (RF) systems include a plurality of power amplifiers having a primary winding and a secondary winding. Each of the power amplifiers may be configured to process signals of different frequency bands. The primary winding for one power amplifier can be detuned while another power amplifier is being used in a transmit mode. By detuning the power amplifier, power coupling from the transmitting power amplifier can be reduced or eliminated.

Abstract: Embodiments of radio frequency (RF) systems include a plurality of power amplifiers having a primary winding and a secondary winding. Each of the power amplifiers may be configured to process signals of different frequency bands. The primary winding for one power amplifier can be detuned while another power amplifier is being used in a transmit mode. By detuning the power amplifier, power coupling from the transmitting power amplifier can be reduced or eliminated.

Abstract: Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures, and a power amplifier and switch can be integrated onto a single complementary metal oxide semiconductor die.

Abstract: Embodiments of radio frequency (RF) systems include a plurality of power amplifiers having a primary winding and a secondary winding. Each of the power amplifiers may be configured to process signals of different frequency bands. The primary winding for one power amplifier can be detuned while another power amplifier is being used in a transmit mode. By detuning the power amplifier, power coupling from the transmitting power amplifier can be reduced or eliminated.

Abstract: Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures. A compensation circuit can act to protect the receive path during an RF transmit mode.

Abstract: Embodiments of radio frequency (RF) systems include a power amplifier having a primary winding and a secondary winding. The primary winding can be biased in different states in transmit and receive modes such that a difference between center frequencies of the primary winding and the secondary winding are significantly different in the different modes.

Abstract: Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures, and a power amplifier and switch can be integrated onto a single complementary metal oxide semiconductor die.

Abstract: Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures. A compensation circuit can act to protect the receive path during an RF transmit mode.

Abstract: Embodiments of radio frequency (RF) systems include a plurality of power amplifiers having a primary winding and a secondary winding. Each of the power amplifiers may be configured to process signals of different frequency bands. The primary winding for one power amplifier can be detuned while another power amplifier is being used in a transmit mode. By detuning the power amplifier, power coupling from the transmitting power amplifier can be reduced or eliminated.

Abstract: Embodiments of radio frequency (RF) systems include a power amplifier having a primary winding and a secondary winding. The primary winding can be biased in different states in transmit and receive modes such that a difference between center frequencies of the primary winding and the secondary winding are significantly different in the different modes.