Patents by Inventor Seug-gab PARK

Seug-gab PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508775
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Shi Li Quan, Hyung-yong Kim, Seug-gab Park, In-gyu Baek, Kyung-rae Byun, Jin-yong Choi
  • Publication number: 20210366974
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gang ZHANG, Shi Li QUAN, Hyung-yong KIM, Seug-gab PARK, In-gyu BAEK, Kyung-rae BYUN, Jin-yong CHOI
  • Patent number: 11183527
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Shi Li Quan, Hyung-yong Kim, Seug-gab Park, In-gyu Baek, Kyung-rae Byun, Jin-yong Choi
  • Publication number: 20200127034
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Application
    Filed: May 13, 2019
    Publication date: April 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gang ZHANG, Shi Li QUAN, Hyung-yong KIM, Seug-gab PARK, ln-gyu BAEK, Kyung-rae BYUN, Jin-yong CHOI