Abstract: A Log-Likelihood Ratio (LLR) combining method and apparatus for Hybrid Automatic Repeat Request (HARQ) in a wireless communication system for reducing a number of the LLR bits of previous packet stored for LLR combining are provided. The LLR combining apparatus includes an LLR combiner for combining a first LLR of a currently received packet and a second LLR of a previously received packet, an LLR buffer for storing the second LLR and a first packet exponent for recovering the second LLR in the same size as the first LLR, and an HARQ controller for determining whether the currently received packet is a retransmission packet or an initial transmission packet, and for controlling the LLR combiner to generate a third LLR by combining the first and second LLRs for the retransmission packet and to bypass the initial transmission packet.

Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.

Abstract: A method and apparatus for decoding a signal in a communication system. The method and apparatus includes receiving a punctured codeword including information bit nodes and unpunctured parity bit nodes; analyzing the unpunctured parity bit nodes, and detecting at least one first block including the unpunctured parity bit nodes among a plurality of blocks each including parity bit nodes having the same importance among all parity bit nodes; and recovering said all parity bit nodes by serial-decoding parity bit nodes included in the first block according to decoding priorities of parity bit nodes, determined by reflecting the first block in a predetermined decoding priority determining algorithm.

Abstract: An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs a node processing operation using information stored in at least one of the node memory and the edge memory, stores a check node value generated by performing the node processing operation in the node memory, and stores a message generated by performing the node processing operation in the edge memory. A switch switches outputs of the node memory and the node processor through a permutation operation. A parity check verifier parity-checks an output from the node memory. A controller provides a control signal for controlling the node processor.

Abstract: A Log-Likelihood Ratio (LLR) combining method and apparatus for Hybrid Automatic Repeat Request (HARQ) in a wireless communication system for reducing a number of the LLR bits of previous packet stored for LLR combining are provided. The LLR combining apparatus includes an LLR combiner for combining a first LLR of a currently received packet and a second LLR of a previously received packet, an LLR buffer for storing the second LLR and a first packet exponent for recovering the second LLR in the same size as the first LLR, and an HARQ controller for determining whether the currently received packet is a retransmission packet or an initial transmission packet, and for controlling the LLR combiner to generate a third LLR by combining the first and second LLRs for the retransmission packet and to bypass the initial transmission packet.

Abstract: A method and apparatus for decoding a signal in a communication system. The method and apparatus includes receiving a punctured codeword including information bit nodes and unpunctured parity bit nodes; analyzing the unpunctured parity bit nodes, and detecting at least one first block including the unpunctured parity bit nodes among a plurality of blocks each including parity bit nodes having the same importance among all parity bit nodes; and recovering said all parity bit nodes by serial-decoding parity bit nodes included in the first block according to decoding priorities of parity bit nodes, determined by reflecting the first block in a predetermined decoding priority determining algorithm.

Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.

Abstract: Disclosed are an apparatus and a method for iterative decoding of a plurality of Frame Error Check (FEC) blocks included in a frame in a wireless communication system. The method includes decoding a first FEC block by considering a first decoding iteration count; determining whether there is another FEC block to be decoded; newly setting a second decoding iteration count for a second FEC block when there is the second FEC block, in such a manner that a number of times of the iterative decoding is actually used for decoding the first FEC block is subtracted from the first decoding iteration count, and the obtained difference value is added to the second decoding iteration count, which has been set for the second FEC block; and decoding the second FEC block by considering the newly set second decoding iteration count.

Abstract: An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs a node processing operation using information stored in at least one of the node memory and the edge memory, stores a check node value generated by performing the node processing operation in the node memory, and stores a message generated by performing the node processing operation in the edge memory. A switch switches outputs of the node memory and the node processor through a permutation operation. A parity check verifier parity-checks an output from the node memory. A controller provides a control signal for controlling the node processor.

Abstract: An apparatus and method for scaling an LLR for an error correction code in a mobile communication system are provided. In the LLR scaling apparatus, an environment factor controller decides an environment factor according to a radio channel environment. A scaling factor generator generates a scaling factor using the environment factor and a received LLR. A multiplier then multiplies the LLR by the scaling factor to scale the LLR.