Patents by Inventor Seul-Ki Oh

Seul-Ki Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210332169
    Abstract: The present invention relates to polyolefin. More specifically, the present invention relates to polyolefin having excellent dart drop impact strength, and exhibiting improved transparency, and such polyolefin has a density of 0.915 g/cm3 to 0.930 g/cm3 measured according to ASTM D1505; and satisfies the following requirements (provided that S1+S2+S3=1), when measuring the relative content of peak area according to melting temperature (Tm) using SSA (Successive Self-nucleation and Annealing) analysis: the content(S1) of peak area at Tm less than 100° C. is 0.33 to 0.35; the content(S2) of peak area at Tm of 100° C. or more and 120° C. or less is 0.52 to 0.56; and the content(S3) of peak area at Tm greater than 120° C. is 0.10 to 0.14.
    Type: Application
    Filed: December 20, 2019
    Publication date: October 28, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Jeongkyu Lee, Sung Min Lee, Hyojoon Lee, Chang Hwan Jang, Sung Ho Park, Seul Ki Im, Jinyoung Lee, Sung Joon Oh, Seyoung Kim, Jisoo Song
  • Patent number: 9711517
    Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Keon Soo Shim, Seul Ki Oh, Eun Seok Choi
  • Publication number: 20170110468
    Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.
    Type: Application
    Filed: March 22, 2016
    Publication date: April 20, 2017
    Inventors: Keon Soo SHIM, Seul Ki OH, Eun Seok CHOI
  • Patent number: 9362305
    Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seul-Ki Oh, Jun-Hyuk Lee
  • Publication number: 20150270283
    Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.
    Type: Application
    Filed: June 9, 2015
    Publication date: September 24, 2015
    Inventors: Seul-Ki OH, Jun-Hyuk LEE
  • Patent number: 9082483
    Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seul-Ki Oh, Jun-Hyuk Lee
  • Patent number: 9076865
    Abstract: A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jun Hyuk Lee, Seul Ki Oh
  • Patent number: 8923072
    Abstract: Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair of first pillars. A pair of second pillars, wherein each second pillar is disposed over a corresponding first pillar, of the pair of the first pillars, and is formed of a semiconductor material. A plurality of word lines and a source selection line form a stack that surrounds the pair of second pillars. A source line is formed over and connected with the pair of second pillars. Drain contacts are formed at both sides of each active region except between pairs of the drain selection lines. A bit line is formed over and connected with the drain contacts.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seul-Ki Oh
  • Publication number: 20140169105
    Abstract: Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair of first pillars. A pair of second pillars, wherein each second pillar is disposed over a corresponding first pillar, of the pair of the first pillars, and is formed of a semiconductor material. A plurality of word lines and a source selection line form a stack that surrounds the pair of second pillars. A source line is formed over and connected with the pair of second pillars. Drain contacts are formed at both sides of each active region except between pairs of the drain selection lines. A bit line is formed over and connected with the drain contacts.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 19, 2014
    Inventor: Seul-Ki OH
  • Publication number: 20140056080
    Abstract: A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.
    Type: Application
    Filed: December 17, 2012
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Jun Hyuk LEE, Seul Ki OH
  • Publication number: 20130215684
    Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 22, 2013
    Inventors: Seul-Ki OH, Jun-Hyuk Lee
  • Publication number: 20110266604
    Abstract: A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit.
    Type: Application
    Filed: December 30, 2010
    Publication date: November 3, 2011
    Inventors: Suk-Goo KIM, Seung-Beck Lee, Jun-Hyuk Lee, Seul-Ki Oh