Abstract: A method of predicting a semiconductor yield includes receiving wafer level data generated by measuring a plurality of wafers, generating a plurality of virtual chips corresponding to the plurality of wafers based on the wafer level data, mapping a test result of the plurality of wafers to the plurality of virtual chips, computing a defect rate of the plurality of virtual chips according to defects based on a result of the mapping, and computing a defect index of the equipment based on the defect rate.

Abstract: A test device includes a memory and a controller. The memory stores reference data including a reference image obtained by photographing a reference pattern on a first semiconductor sample, a first height of the reference pattern, a first shadow length of the reference pattern, and a reference value that represents a correlation between the first height and the first shadow length. The controller receives an image obtained by photographing a pattern on a second semiconductor sample, measures a second shadow length of the pattern from the image, and calculates a second height of the pattern from the second shadow length based on the reference data.

Abstract: A method of detecting clusters of defects includes measuring each of a plurality of wafers to obtain a plurality of wafer level maps of a plurality of wafer measurement points, creating a composite wafer level map by combining the plurality of wafer level maps, dividing the composite wafer level map into a plurality of grid areas, obtaining a plurality of target grid areas from the plurality of grid areas using unique values of the plurality of grid areas, grouping the plurality of target grid areas into a plurality of target grid clusters corresponding to the clusters of defects, and obtaining a detection priority for each of the plurality of target grid clusters based on the unique value of the plurality of target grid areas included in the plurality of target grid clusters.

Abstract: A defect detection device includes: a memory configured to store a layout image indicating a circuit pattern and indicating a dummy pattern; and a controller comprising an artificial neural network configured to learn the layout image, the controller being configured to: determine, based on an inspection image obtained by photographing an area including a defect on a wafer, whether the defect is in a first area in which the circuit pattern is positioned or in a second area in which the dummy pattern is positioned, by using the artificial neural network, and determine a type of the defect based on whether the defect is positioned is in the first area or in the second area.

Abstract: A method of detecting defects of a wafer including generating a composite wafer map comprising defect points by combining a plurality of wafer level maps generated by measuring the wafer according to the respective process operations; sorting the defect points according to defect clusters using positions of the defect points included in the composite wafer map; and detecting an initial process operation, from among the respective process operations, in which a defect occurred, using operation information, for each of the defect clusters.