Abstract: A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.

Abstract: A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads.