Abstract: A vertical memory device includes a memory cell structure extending primarily in a vertical direction. A resistive layer is electrically connected to a first end of the memory cell structure. A selector is electrically connected to a second end of the memory cell structure and includes a variable resistive material of which an electrical resistive value is reversibly changed in response to an electrical signal. A first bit line is located apart from the memory cell structure in the vertical direction with the resistive layer disposed therebetween and is connected to the resistive layer. A second bit line is located apart from the memory cell structure in the vertical direction with the selector disposed therebetween and is connected to the selector. A plurality of word line plates are spaced apart from each other in the vertical direction and overlapping each other in the vertical direction. Each word line plate at least partially surrounds a portion of a sidewall of the memory cell structure.

Abstract: A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, and a memory cell extending in a vertical direction between the first conductive line and the second conductive line. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer, which are sequentially stacked on the first conductive line. The switching pattern includes a chalcogenide layer including a chalcogen element of group VI of the periodic table, and an element of group IV and an element of group V of the periodic table, which are chemically bonded to the group VI chalcogen element. The switching pattern is configured to have a three-level concentration gradient of the group IV element or the group V element in the vertical direction.

Abstract: A semiconductor device includes a stack structure that includes horizontal conductive layers and interlayer insulating layers that are alternately stacked with each other in a first direction, vertical conductive layers that pass through the stack structure and extend in the first direction, where the vertical conductive layers have a pillar shape, selector layers that surround external surfaces of the vertical conductive layers, where the selector layers include a chalcogenide material, and first isolation layers that divide the horizontal conductive layers from each other and pass through the stack structure and between the vertical conductive layers adjacent to each other in a second direction that is perpendicular to the first direction. Ends of the first isolation layers in the second direction are in contact with external surfaces of the selector layers.

Abstract: A semiconductor memory device includes a semiconductor substrate; a plurality of word line layers on the semiconductor substrate, each word line layer of the plurality of word line layers including an insulating line and a word line; a plurality of insulating layers in spaces between the plurality of word line layers, the plurality of insulating layers being apart from each other in a vertical direction on the semiconductor substrate; a channel structure extending in the vertical direction on the semiconductor substrate, the channel structure including a channel region and a gate dielectric layer surrounding the channel region; and a bit line on the channel structure, the bit line extending in a first horizontal direction perpendicular to the vertical direction and being connected to the channel structure, wherein the word line of each word line layer of the plurality of word line layers has a meandering shape.

Abstract: A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.

Abstract: A semiconductor-device inspection apparatus includes a stage configured to allow a measurement target to be placed thereon, an actuator configured to move the stage in a vertical direction, a detector configured to detect a plurality of Raman spectra from scattered light that has been scattered away from the measurement target, and a processor configured to generate a plurality of spectral images for a measurement variable by using the plurality of Raman spectra detected by the detector, wherein the detector is further configured to detect the plurality of Raman spectra at different vertical levels of the measurement target.

Abstract: A self-selecting memory device includes a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell. The first memory cell includes a first electrode, a first switching memory unit and a second electrode sequentially and vertically stacked. The second memory cell includes a third electrode, a second switching memory unit and a fourth electrode sequentially and vertically stacked. The first switching memory unit includes a first SSM pattern contacting an upper surface of the first electrode and including an OTS material, and a first nitrogen-containing pattern contacting an upper surface of the first SSM pattern and a lower surface of the second electrode and including an OTS material doped with nitrogen.

Abstract: A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.

Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.

Abstract: A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.

Abstract: A variable resistance memory device includes a substrate. A first conductive line is disposed on the substrate and extends primarily in a first direction. A second conductive line is disposed on the substrate and extends primarily in a second direction. The second direction intersects the first direction. A phase change pattern is disposed between the first conductive line and the second conductive line. A bottom electrode is disposed between the phase change pattern and the first bottom electrode includes first a first sidewall segment that connects the first conductive line and the phase change pattern to each other. The phase change pattern has a width in the first direction that decreases toward the substrate. The first sidewall segment has a first lateral surface and a second lateral surface that face each other. A lowermost portion of the phase change pattern is disposed between the first lateral surface and the second lateral surface.

Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.

Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines.

Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

Abstract: A variable resistance memory device includes a substrate. A first conductive line is disposed on the substrate and extends primarily in a first direction. A second conductive line is disposed on the substrate and extends primarily in a second direction. The second direction intersects the first direction. A phase change pattern is disposed between the first conductive line and the second conductive line. A bottom electrode is disposed between the phase change pattern and the first bottom electrode includes first a first sidewall segment that connects the first conductive line and the phase change pattern to each other. The phase change pattern has a width in the first direction that decreases toward the substrate. The first sidewall segment has a first lateral surface and a second lateral surface that face each other. A lowermost portion of the phase change pattern is disposed between the first lateral surface and the second lateral surface.

Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures.

Abstract: A variable resistance memory device may include a word line extending in a first direction, a bit line extending in a second direction crossing the first direction, a phase-changeable pattern provided between the word line and the bit line, a bottom electrode provided between the phase-changeable pattern and the word line, and a spacer provided on a side surface of the bottom electrode and between the phase-changeable pattern and the word line. The bottom electrode may include a first portion and a second portion, and the second portion is provided between the first portion and the spacer. The first and second portions of the bottom electrodes may have different lengths from each other in the second direction.

Abstract: A variable resistance memory device may include a word line extending in a first direction, a bit line extending in a second direction crossing the first direction, a phase-changeable pattern provided between the word line and the bit line, a bottom electrode provided between the phase-changeable pattern and the word line, and a spacer provided on a side surface of the bottom electrode and between the phase-changeable pattern and the word line. The bottom electrode may include a first portion and a second portion, and the second portion is provided between the first portion and the spacer. The first and second portions of the bottom electrodes may have different lengths from each other in the second direction.