Patents by Inventor Seulye KIM
Seulye KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11910607Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.Type: GrantFiled: August 5, 2022Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Kim, Sunggil Kim, Dongkyum Kim, Seulye Kim, Ji-Hoon Choi
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Patent number: 11792993Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conducType: GrantFiled: July 7, 2022Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Junghwan Kim, Chanhyoung Kim
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Patent number: 11737277Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: GrantFiled: November 10, 2021Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
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Patent number: 11711920Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.Type: GrantFiled: October 21, 2020Date of Patent: July 25, 2023Inventors: Sunggil Kim, Seulye Kim, Jung-Hwan Kim
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Patent number: 11626414Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.Type: GrantFiled: June 16, 2020Date of Patent: April 11, 2023Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Jung-Hwan Kim, Chan-Hyoung Kim
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Patent number: 11600638Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.Type: GrantFiled: December 29, 2020Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Lee, Sunggil Kim, Seulye Kim, Hwaeon Shin, Joonsuk Lee, Hyeeun Hong
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Publication number: 20220384482Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan KIM, Sunggil KIM, Dongkyum KIM, Seulye KIM, Ji-Hoon CHOI
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Publication number: 20220352203Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base, layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure arid a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the condType: ApplicationFiled: July 7, 2022Publication date: November 3, 2022Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Junghwan Kim, Chanhyoung Kim
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Patent number: 11430800Abstract: A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.Type: GrantFiled: April 3, 2020Date of Patent: August 30, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sunggil Kim, Seulye Kim, Dongkyum Kim, Sungjin Kim, Junghwan Kim, Chanhyoung Kim, Jihoon Choi
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Patent number: 11424264Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.Type: GrantFiled: April 2, 2020Date of Patent: August 23, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Kim, Sunggil Kim, Dongkyum Kim, Seulye Kim, Ji-Hoon Choi
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Patent number: 11387253Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conducType: GrantFiled: June 24, 2020Date of Patent: July 12, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Junghwan Kim, Chanhyoung Kim
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Publication number: 20220139956Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon CHOI, Sunggil KIM, Seulye KIM, HongSuk KIM, Phil Ouk NAM, Jaeyoung AHN
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Patent number: 11282856Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.Type: GrantFiled: April 10, 2020Date of Patent: March 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, HongSuk Kim, Phil Ouk Nam, Jaeyoung Ahn
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Publication number: 20220068968Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: Ji Hoon CHOI, Sung Gil KIM, Seulye KIM, Jung Ho KIM, Hong Suk KIM, Phil Ouk NAM, Jae Young AHN, Han Jin LIM
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Patent number: 11189636Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: GrantFiled: May 8, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
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Publication number: 20210305276Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.Type: ApplicationFiled: October 21, 2020Publication date: September 30, 2021Inventors: Sunggil Kim, Seulye Kim, Jung-Hwan Kim
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Publication number: 20210118907Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.Type: ApplicationFiled: December 29, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon LEE, SUNGGIL KIM, SEULYE KIM, HWAEON SHIN, JOONSUK LEE, HYEEUN HONG
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Publication number: 20210098480Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.Type: ApplicationFiled: June 16, 2020Publication date: April 1, 2021Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Jung-Hwan Kim, Chan-Hyoung Kim
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Patent number: 10950612Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.Type: GrantFiled: May 17, 2018Date of Patent: March 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sunggil Kim, Sangsoo Lee, Seulye Kim, Hongsuk Kim, Jintae Noh, Ji-Hoon Choi, Jaeyoung Ahn, Sanghoon Lee
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Publication number: 20210057445Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conducType: ApplicationFiled: June 24, 2020Publication date: February 25, 2021Inventors: Sunggil KIM, Sungjin KIM, Seulye KIM, Junghwan KIM, Chanhyoung KIM