Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: Electronic devices, displays, and methods are provided for performing row shuffling to reduce an appearance of image artifacts during eye movements such as saccades. An electronic display may include a number of rows of display pixels and driving circuitry to drive the rows of pixels. The driving circuitry may spatially shuffle or temporally shuffle, or both spatially and temporally shuffle, a row order of driving the rows of display pixels.

Abstract: The present disclosure is directed to estimating and modulating peak luminance of the display substantially in real-time to allow very bright pixels to be shown on the electronic display as long as the total electrical energy drawn by the electronic display does not exceed a threshold. The amount of electrical energy that is being drawn by the electronic display may be estimated from the image data by counting the number of rows of pixels that are emitting pulses in discrete bins of time. Because the pulses draw a predictable amount of electrical energy per row per time bin, the amount of electrical energy drawn by the electronic display may be estimated substantially in real time. The image data on the electronic display may therefore be modulated to avoid drawing too much electrical energy from the power source of the electronic device while permitting a high dynamic range.

Abstract: A control circuit adjusts a value of a source supply voltage VSSEL provided to a display area in an electronic display. The control circuit also adjusts a voltage Vreset applied to the display area to cause the display area to emit light more uniformly under various ambient conditions (e.g., temperature) surrounding the display area. Dynamically changing Vreset is employed to make anode charging dynamics independent of temperature. The control circuit adjusts the source supply voltage VSSEL and the voltage Vreset together to compensate display pixel hysteresis effects and display artifacts caused by temperature changes and brightness changes of the display area and collectively produce images. Dynamically tuning the Vreset and the VSSEL voltages also saves power and improves gray level accuracy for the electronic display.

Abstract: An electronic device may display image content via a tile-based display by controlling light emission from display pixels of the tile-based display. Based on image data associated with the image content, a processing circuitry of the tile-based display may receive a potential tile boundary. The processing circuitry may resample the image data based on geometry of the tile boundary and positions of the display pixels on the tile-based panel. After resampling the image data, the processing circuitry may adjust gain of the tile boundary display pixels according to a gain mask to compensate for the tile boundary.

Abstract: An electronic device may display image content via a tile-based display by controlling light emission from display pixels of the tile-based display. Based on image data associated with the image content, a processing circuitry of the tile-based display may receive a potential tile boundary. The processing circuitry may resample the image data based on geometry of the tile boundary and positions of the display pixels on the tile-based panel. After resampling the image data, the processing circuitry may adjust gain of the tile boundary display pixels according to a gain mask to compensate for the tile boundary.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.