Patents by Inventor Seung-beom Yoon

Seung-beom Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7492000
    Abstract: Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least a portion of the associated floating gate with the size of the projecting portion being determined by a first sacrificial polysilicon spacer that, when removed, produces a concave region in an intermediate insulating structure. The control gate is then formed as a polysilicon spacer adjacent the intermediate insulating structure, the portion of the spacer extending into the concave region determining the dimension and spacing of the projecting portion and the thickness of the interpoly oxide (IPO) separating the upper portions of the split-gate electrodes thereby providing improved performance and manufacturability.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee Seog Jeon, Seung Beom Yoon, Yong Tae Kim
  • Publication number: 20090011589
    Abstract: A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.
    Type: Application
    Filed: September 17, 2008
    Publication date: January 8, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hee-seog JEON, Seung-beom YOON
  • Publication number: 20080318406
    Abstract: In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
    Type: Application
    Filed: August 19, 2008
    Publication date: December 25, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Publication number: 20080315289
    Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.
    Type: Application
    Filed: August 27, 2008
    Publication date: December 25, 2008
    Inventors: JAE HWANG KIM, SEUNG-BEOM YOON, KWANG-WOOK KOH, CHANG-HUN LEE, SUNG-HO KIM, SUNG-CHUL PARK, JU-RI KIM
  • Patent number: 7432159
    Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Kim, Seung-Beom Yoon, Kwang-Wook Koh, Chang-Hun Lee, Sung-Ho Kim, Sung-Chul Park, Ju-Ri Kim
  • Patent number: 7429766
    Abstract: In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 7422949
    Abstract: The present invention relates to a high voltage transistor and method of manufacturing the same.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: September 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-kwang Yu, Hee-seog Jeon, Seung-beom Yoon, Yong-tae Kim
  • Patent number: 7411243
    Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: August 12, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sam Park, Seung-Beom Yoon, Jeong-Uk Han, Sung-Taeg Kang, Seung-Jin Yang
  • Patent number: 7397079
    Abstract: A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Yong-Suk Choi, Seung-Beom Yoon, Yong-Tae Kim, Jin-Woo Kim
  • Publication number: 20080132014
    Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.
    Type: Application
    Filed: February 4, 2008
    Publication date: June 5, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoo, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-tae Kim, Jeong-wook Han
  • Publication number: 20080128783
    Abstract: A split-gate non-volatile memory device includes a raised oxide layer on a field oxide region between adjacent split-gate memory cells, the raised oxide layer extending onto first and second floating gates included in the adjacent split-gate memory cells covered by a wordline electrically coupled to respective control gates included in the adjacent split-gate memory cells.
    Type: Application
    Filed: February 7, 2008
    Publication date: June 5, 2008
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 7352026
    Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoo, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-tae Kim, Jeong-wook Han
  • Patent number: 7351636
    Abstract: A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first and second adjacent floating gates from one another. A control gate is formed on the oxide layer on the first and second adjacent floating gates. Related devices are also disclosed.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 7345336
    Abstract: A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: March 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-seog Jeon, Seung-beom Yoon, Yong-tae Kim
  • Publication number: 20080029808
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 7, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Seog JEON, Seung-Beom YOON, Jeong-Uk HAN
  • Patent number: 7323740
    Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han
  • Patent number: 7320913
    Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: January 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Taeg Kang, Hyok-Ki Kwon, Bo Young Seo, Seung Beom Yoon, Hee Seog Jeon, Yong-Suk Choi, Jeong-Uk Han
  • Patent number: 7315057
    Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: January 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee Seog Jeon, Sung-Taeg Kang, Hyok-Ki Kwon, Yong Tae Kim, BoYoung Seo, Seung Beom Yoon, Jeong-Uk Han
  • Publication number: 20070298571
    Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.
    Type: Application
    Filed: September 4, 2007
    Publication date: December 27, 2007
    Inventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han
  • Patent number: 7285820
    Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 23, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Park, Seung-Beom Yoon, Jeong-Uk Han, Seong-Gyun Kim, Sung-Taeg Kang, Bo-Young Seo, Sang-Woo Kang, Sung-Woo Park