Patents by Inventor Seung-Bong Kim
Seung-Bong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145263Abstract: According to an aspect of the present disclosure, there is provided a substrate treating apparatus comprising: a vessel part having a substrate treatment region formed therein and including a supply port through which a treating fluid is supplied to the substrate treatment region and an exhaust port through which the treating fluid is exhausted from the substrate treatment region; a fluid supply unit configured to supply the treating fluid to the substrate treatment region; an exhaust unit configured to exhaust the treating fluid from the vessel part. The exhaust unit comprises: a main line connected to the exhaust port; an extension line branched from at least one of first and second nodes of the main line and including at least one of a first orifice or a first check valve to control an exhaust speed; and an auxiliary line branched from a third node of the main line, where an orifice and a check valve are not formed.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Inventors: Seung Hoon OH, Ki Bong KIM, Jong Doo LEE, Young Hun LEE, Mi So PARK, Jin Se PARK, Yong Sun KO
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Publication number: 20240129648Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Yu Jin PARK, Nam Ryeol KIM, Kang Bong SEO, Jeong Eun SONG, Jung Soon SHIN, Seung Hwan LEE
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Patent number: 10020030Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.Type: GrantFiled: February 19, 2016Date of Patent: July 10, 2018Assignee: SK hynix Inc.Inventors: Seung Bong Kim, Geun Il Lee
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Publication number: 20170125072Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.Type: ApplicationFiled: February 19, 2016Publication date: May 4, 2017Inventors: Seung Bong KIM, Geun Il LEE
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Patent number: 9159399Abstract: A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode.Type: GrantFiled: September 7, 2012Date of Patent: October 13, 2015Assignee: SK Hynix Inc.Inventor: Seung-Bong Kim
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Patent number: 8559254Abstract: A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.Type: GrantFiled: July 7, 2011Date of Patent: October 15, 2013Assignee: Hynix Semiconductor Inc.Inventor: Seung-Bong Kim
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Publication number: 20130163351Abstract: A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode.Type: ApplicationFiled: September 7, 2012Publication date: June 27, 2013Inventor: Seung-Bong KIM
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Patent number: 8120972Abstract: A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals.Type: GrantFiled: April 28, 2009Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventor: Seung Bong Kim
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Publication number: 20120008446Abstract: A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.Type: ApplicationFiled: July 7, 2011Publication date: January 12, 2012Inventor: Seung-Bong KIM
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Patent number: 8081534Abstract: A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses, a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to the row addresses and column addresses, and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses.Type: GrantFiled: June 24, 2009Date of Patent: December 20, 2011Assignee: Hynix Semiconductor Inc.Inventor: Seung-Bong Kim
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Publication number: 20100296357Abstract: A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses, a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to the row addresses and column addresses, and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses.Type: ApplicationFiled: June 24, 2009Publication date: November 25, 2010Inventor: Seung-Bong Kim
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Patent number: 7729187Abstract: A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second precharge element for precharging a fourth bit line in response to a third precharge signal.Type: GrantFiled: June 30, 2008Date of Patent: June 1, 2010Assignee: Hynix Semiconductor Inc.Inventor: Seung Bong Kim
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Publication number: 20100128540Abstract: A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals.Type: ApplicationFiled: April 28, 2009Publication date: May 27, 2010Inventor: Seung Bong KIM
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Patent number: 7705651Abstract: A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as an output signal, wherein the delay time can be one selected from a plurality of delay times according to the sensing signal. The delay time can be selectively determined according to a clock frequency used in a semiconductor memory apparatus.Type: GrantFiled: January 14, 2008Date of Patent: April 27, 2010Assignee: Hynix Semiconductor Inc.Inventor: Seung Bong Kim
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Patent number: 7639555Abstract: A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal, a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage, and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not.Type: GrantFiled: December 30, 2008Date of Patent: December 29, 2009Assignee: Hynix Semiconductor Inc.Inventor: Seung Bong Kim
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Publication number: 20090303818Abstract: A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal, a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage, and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not.Type: ApplicationFiled: December 30, 2008Publication date: December 10, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Seung Bong Kim
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Patent number: 7596049Abstract: The semiconductor memory device includes a plurality of bank groups each including a plurality of banks sharing one of a plurality of global input/output line groups, a data input unit configured to transfer external data to data input global lines in response to write commands corresponding to the respective bank groups, a data output unit configured to output data applied on data output global lines to an external circuit in response to read commands corresponding to the respective bank groups, and a data transfer unit configured to transfer data applied on the data input global lines to one of the plurality of global input/output line groups in response to the write commands, and to transfer data applied on one of the plurality of global input/output line groups to the data output global lines in response to the read commands.Type: GrantFiled: November 30, 2007Date of Patent: September 29, 2009Assignee: Hynix Semiconductor, Inc.Inventors: Young-Han Jeong, Seung-Bong Kim
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Publication number: 20090238019Abstract: A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second precharge element for precharging a fourth bit line in response to a third precharge signal.Type: ApplicationFiled: June 30, 2008Publication date: September 24, 2009Inventor: Seung Bong Kim
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Publication number: 20090039932Abstract: A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as an output signal, wherein the delay time can be one selected from a plurality of delay times according to the sensing signal. The delay time can be selectively determined according to a clock frequency used in a semiconductor memory apparatus.Type: ApplicationFiled: January 14, 2008Publication date: February 12, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Seung Bong Kim
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Publication number: 20080144404Abstract: The semiconductor memory device includes a plurality of band groups each including a plurality of banks sharing one of a plurality of global input/output line groups, a data input unit configured to transfer external data to data input global lines in response to write commands corresponding to the respective bank groups, a data output unit configured to output data applied on data output global lines to an external circuit in response to read commands corresponding to the respective bank groups, and a data transfer unit configured to transfer data applied on the data input global lines to one of the plurality of global input/output line groups in response to the write commands, and to transfer data applied on one of the plurality of global input/output line groups to the data output global lines in response to the read commands.Type: ApplicationFiled: November 30, 2007Publication date: June 19, 2008Inventors: Young-Han Jeong, Seung-Bong Kim