Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: A semiconductor memory device includes both a data redundancy memory cell array and a local redundancy memory cell array. Cells of the data redundancy memory cell array and/or cells the local redundancy memory cell arrays may be substituted for one or more defective cells of a normal memory cell array, depending on the number of defects generated in the normal memory cell array. An embodiment of a semiconductor memory device may include a plurality of normal memory blocks, each normal memory block comprising a normal memory cell array and a local redundancy memory cell array, at least one data line redundancy memory block, each data line redundancy memory block comprising a data redundancy memory cell array, and a redundancy controller to substitute columns of the data line redundancy memory cell array for some columns of at least two columns in each normal memory cell array, and to substitute columns of the local redundancy memory cell array for the remaining columns of the at least two columns.

Abstract: A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.

Abstract: Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.

Abstract: Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers.

Abstract: A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.

Abstract: Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers.

Abstract: Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.

Abstract: A data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. A clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. A clock buffer control circuit is responsive to the read cycle control signal and to the clock signal and transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval.

Abstract: A data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. A clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. A clock buffer control circuit is responsive to the read cycle control signal and to the clock signal and transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval.