Patents by Inventor Seung-Chul Song
Seung-Chul Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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METHOD OF CMOS MANUFACTURING UTILIZING MULTI-LAYER EPITAXIAL HARDMASK FILMS FOR IMPROVED EPI PROFILE
Publication number: 20150031177Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.Type: ApplicationFiled: July 25, 2013Publication date: January 29, 2015Applicant: Texas Instruments IncorporatedInventors: Deborah Jean RILEY, Seung-Chul SONG -
Publication number: 20140315361Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.Type: ApplicationFiled: July 8, 2014Publication date: October 23, 2014Inventors: Hiroaki Niimi, Seung-Chul Song
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Patent number: 8803253Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.Type: GrantFiled: September 11, 2012Date of Patent: August 12, 2014Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Seung-Chul Song
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Patent number: 8796777Abstract: A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.Type: GrantFiled: September 2, 2009Date of Patent: August 5, 2014Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han
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Publication number: 20140183663Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Seung-Chul Song, James W. Blatchford, Kwan-Yong Lim
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Patent number: 8691644Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.Type: GrantFiled: July 5, 2012Date of Patent: April 8, 2014Assignee: Texas Instruments IncorporatedInventors: Seung-Chul Song, Amitabh Jain, Deborah J. Riley
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Publication number: 20140070327Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hiroaki Niimi, Seung-Chul Song
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Publication number: 20140011340Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Inventors: Seung-Chul Song, Amitabh Jain, Deborah J. Riley
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Patent number: 8447547Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.Type: GrantFiled: June 17, 2009Date of Patent: May 21, 2013Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Seung-Chul Song, Hyunkook Park
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Publication number: 20120256270Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.Type: ApplicationFiled: June 18, 2012Publication date: October 11, 2012Applicant: International Business Machines CorporationInventors: Byoung H. Lee, Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi, Jong Hoan Sim, Seung-Chul Song, Zhibo Zhang
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Patent number: 8236686Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.Type: GrantFiled: May 30, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Byoung H. Lee, Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi, Jong Hoan Sim, Seung-Chul Song, Zhibo Zhang
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Publication number: 20120113708Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
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Patent number: 8130534Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.Type: GrantFiled: January 8, 2009Date of Patent: March 6, 2012Assignee: QUALCOMM IncorporatedInventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
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Publication number: 20110235406Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Publication number: 20110051535Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.Type: ApplicationFiled: September 2, 2009Publication date: March 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Seung-Chul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Publication number: 20100324850Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.Type: ApplicationFiled: June 17, 2009Publication date: December 23, 2010Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Seung-Chul Song, Hyunkook Park
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Publication number: 20100308408Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.Type: ApplicationFiled: June 3, 2009Publication date: December 9, 2010Applicant: QUALCOMM INCORPORATEDInventors: Seung-Chul Song, Beom-Mo Han, Mohamed Hassan Abu-Rahma
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Patent number: 7829951Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.Type: GrantFiled: November 6, 2008Date of Patent: November 9, 2010Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Publication number: 20100172173Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.Type: ApplicationFiled: January 8, 2009Publication date: July 8, 2010Applicant: QUALCOMM INCORPORATEDInventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
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Patent number: 7741168Abstract: Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.Type: GrantFiled: July 25, 2007Date of Patent: June 22, 2010Assignee: Sematech, Inc.Inventors: Seung-Chul Song, Joel Barnett, Byong Sun Ju