Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion.

Abstract: A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

Abstract: In a method of manufacturing a semiconductor package, a semiconductor chip including a circuit unit that has a first circuit and a second circuit spaced apart from each other, a first conductive member for electrically connecting the first circuit to the second circuit and a cut-out portion for disconnecting the first and second circuits may be prepared. A test signal may be applied to the first circuit and the second circuit through the first conductive member to test the first and second circuits. The cut-out portion may be selectively removed in accordance with test results to divide the first conductive member into a first sub-conductive member electrically connected to the first circuit and a second sub-conductive member electrically connected to the second circuit. The first and second sub-conductive members may then be electrically connected to each other using a second conductive member.

Abstract: An embodiment includes a dual interconnection form in which power/ground pads and signal pads of a semiconductor chip are electrically connected to a package substrate in different connection manners. First connection members that electrically connect the power/ground pads with the substrate have relatively large cross-sectional dimensions in comparison to its length, for example, solder bumps or gold bumps. Second connection members that electrically connect the signal pads with the substrate have relatively small cross-sectional dimensions in comparison its length, for example, conductive wires or beam leads. Such different ways of electrically connecting different kinds of pads with the substrate realize the most suitable electrical performance, effectively meeting the needs of high speed and low power consumption of the semiconductor devices.

Abstract: The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

Abstract: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

Abstract: Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion.

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.